x86-64.net

Instruction

VMINMAXBF16

Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed bfloat16 values, as an immediate selects, with sign control.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMINMAXBF16 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMINMAXBF16 xmm {k}{z}, xmm, xmm, imm8 VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_XMMbf16_IMM8_AVX512EVEX.128.F2.0F3A.W0 52 /r ibAVX10.2
VMINMAXBF16 xmm {k}{z}, xmm, m128/m16bcst, imm8 VMINMAXBF16_XMMbf16_MASKmskw_XMMbf16_MEMbf16_IMM8_AVX512EVEX.128.F2.0F3A.W0 52 /r ibAVX10.2
VMINMAXBF16 ymm {k}{z}, ymm, ymm, imm8 VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_YMMbf16_IMM8_AVX512EVEX.256.F2.0F3A.W0 52 /r ibAVX10.2
VMINMAXBF16 ymm {k}{z}, ymm, m256/m16bcst, imm8 VMINMAXBF16_YMMbf16_MASKmskw_YMMbf16_MEMbf16_IMM8_AVX512EVEX.256.F2.0F3A.W0 52 /r ibAVX10.2
VMINMAXBF16 zmm {k}{z}, zmm, zmm, imm8 VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_ZMMbf16_IMM8_AVX512EVEX.512.F2.0F3A.W0 52 /r ibAVX10.2
VMINMAXBF16 zmm {k}{z}, zmm, m512/m16bcst, imm8 VMINMAXBF16_ZMMbf16_MASKmskw_ZMMbf16_MEMbf16_IMM8_AVX512EVEX.512.F2.0F3A.W0 52 /r ibAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_minmax_pbh __m128bh _mm_minmax_pbh(__m128bh A, __m128bh B, const int C)

VMINMAXBF16 xmm, xmm, xmm, imm8 EVEX.128 -mavx10.2

VMINMAXBF16 xmm, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2with AVX enabled

_mm_mask_minmax_pbh __m128bh _mm_mask_minmax_pbh(__m128bh W, __mmask8 U, __m128bh A, __m128bh B, const int C)

VMINMAXBF16 xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx512bf16 -mavx512vl -mavx10.2

VMINMAXBF16 xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx -mavx512bf16 -mavx512vl -mavx10.2with AVX enabled

_mm_maskz_minmax_pbh __m128bh _mm_maskz_minmax_pbh(__mmask8 U, __m128bh A, __m128bh B, const int C)

VMINMAXBF16 xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx512bf16 -mavx512vl -mavx10.2

VMINMAXBF16 xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx -mavx512bf16 -mavx512vl -mavx10.2with AVX enabled

_mm256_minmax_pbh __m256bh _mm256_minmax_pbh(__m256bh A, __m256bh B, const int C)

VMINMAXBF16 ymm, ymm, ymm, imm8 EVEX.256 -mavx10.2

VMINMAXBF16 ymm, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2with AVX enabled

_mm256_mask_minmax_pbh __m256bh _mm256_mask_minmax_pbh(__m256bh W, __mmask16 U, __m256bh A, __m256bh B, const int C)

VMINMAXBF16 ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx512bf16 -mavx512vl -mavx10.2

VMINMAXBF16 ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx -mavx512bf16 -mavx512vl -mavx10.2with AVX enabled

_mm256_maskz_minmax_pbh __m256bh _mm256_maskz_minmax_pbh(__mmask16 U, __m256bh A, __m256bh B, const int C)

VMINMAXBF16 ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx512bf16 -mavx512vl -mavx10.2 -mavx

VMINMAXBF16 ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx -mavx512bf16 -mavx512vl -mavx10.2with AVX enabled

_mm512_minmax_pbh __m512bh _mm512_minmax_pbh(__m512bh A, int B, const int C)

VMINMAXBF16 zmm, zmm, zmm, imm8 EVEX.512 -mavx10.2

VMINMAXBF16 zmm, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_mask_minmax_pbh __m512bh _mm512_mask_minmax_pbh(__m512bh W, __mmask32 U, __m512bh A, __m512bh B, const int C)

VMINMAXBF16 zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx512bf16 -mavx10.2

VMINMAXBF16 zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx -mavx512bf16 -mavx10.2with AVX enabled

_mm512_maskz_minmax_pbh __m512bh _mm512_maskz_minmax_pbh(__mmask32 U, __m512bh A, __m512bh B, const int C)

VMINMAXBF16 zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx512bf16 -mavx10.2 -mavx512f

VMINMAXBF16 zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx -mavx512bf16 -mavx10.2 -mavx512fwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_MINMAX_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MINMAX_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MINMAX_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.