VMINMAXBF16

VMINMAXBF16 applies one of the eight IEEE 754-2019 minimum and maximum operations to each pair of bfloat16 values in two vectors, 8, 16 or 32 pairs, with the immediate that VMINMAXPS’s page decodes. Its opcode is 52h in EVEX map 0F3A with an F2 prefix and W0; it takes a write mask and a broadcast value from memory, but no {sae}. The rules for NaNs and signed zeros are those on VMINMAXPD’s page.

No exceptions, no denormals#

Like AVX10.2’s other bfloat16 arithmetic, it neither reads nor writes MXCSR: the AVX10.2 specification (revision 7.0) gives it no exceptions, not even for a signaling NaN, and treats denormal inputs as zeros and flushes denormal results whatever DAZ and FTZ say. Two tiny values of the same sign therefore compare equal, and the result is zero.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 vectorizes a loop over __bf16 arrays computing __builtin_elementwise_minimum into VMINMAXBF16 with immediate 4, the second source from memory. For a single __bf16 it widens both values to floats, uses VMINMAXSS and narrows with VCVTNEPS2BF16, which keeps denormals, so the vector and scalar code can disagree on them.

In Clang 23.1.2’s avx10_2_512minmaxintrin.h, _mm512_minmax_pbh(A, B, C) passes A for both sources, so _mm512_minmax_pbh(a, b, 0) compiles to vminmaxbf16 zmm0, zmm0, zmm0, 0; the masked 512-bit forms inherit it, while the 128- and 256-bit forms pass both. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.bf16[i]
        b = src3.bf16[i]
        zmm1.bf16[i] = fminmax(a, b, imm8)
    elif zeroing:
        zmm1.bf16[i] = 0
    # else: zmm1.bf16[i] keeps its value
# imm8[1:0]: min, max, min |x|, max |x|; bit 4: a NaN yields; [3:2]: sign of a, own, 0, 1
# m16bcst: src3.bf16[i] is the m16 for every i
# BF16: to nearest even, denormals flushed, no flags; MXCSR unused
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; denormal inputs read as zero; denormal results flushed to zero

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXBF16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VCVTTSS2USIS
• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS

All 96 AVX10.2 instructions