VMINMAXPD

VMINMAXPD applies one of the eight IEEE 754-2019 minimum and maximum operations to each pair of doubles in two vectors, the operation and the sign of the result chosen by an immediate byte that VMINMAXPS’s page decodes. It belongs to AVX10.2: opcode 52h in EVEX map 0F3A with a 66 prefix and W1 (VMINMAXPS has W0), on 128, 256 or 512 bits, with a write mask, a broadcast double from memory, and {sae} on the 512-bit form. VMINMAXSD handles one double.

NaNs, zeros and equal magnitudes#

The AVX10.2 specification (revision 7.0) settles each case in tables. For minimum, maximum and their magnitude forms, a NaN in either source gives that NaN, quieted; of two NaNs the first source’s wins unless only the second is signaling. The “Number” forms return the other source when only one is a NaN, quiet or signaling. -0 counts as less than +0, so a minimum of the two zeros is -0 and a maximum +0, and of two values of the same magnitude and opposite signs the magnitude forms return the negative one for a minimum and the positive one for a maximum. A signaling NaN raises the invalid exception, a denormal input the denormal one when neither input is a NaN, and DAZ applies as MXCSR says. One footnote of the specification limits that exception for the “Number” forms to two NaN inputs, against its operation table and the tables of NaN results.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 vectorizes a loop over double arrays computing __builtin_elementwise_minimum(a[i], b[i]) into VMINMAXPD with immediate 4 on zmm registers, the second source from memory, and __builtin_fmaximum_num into immediate 15h. C’s fmin instead becomes VMINPD, VCMPUNORDPD and a masked move, and a[i] < b[i] ? a[i] : b[i] a bare VMINPD. _mm512_minmax_pd(a, b, 0x11) gives vminmaxpd zmm0, zmm0, zmm1, 17. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = fminmax(a, b, imm8)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# imm8[1:0]: min, max, min |x|, max |x|; bit 4: a NaN yields; [3:2]: sign of a, own, 0, 1
# m64bcst: src3.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VDIVBF16
• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD

All 96 AVX10.2 instructions