x86-64.net

Instruction

VMINMAXPD

Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed doubles, as an immediate selects, with sign control.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMINMAXPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMINMAXPD xmm {k}{z}, xmm, xmm, imm8 VMINMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512EVEX.128.66.0F3A.W1 52 /r ibAVX10.2
VMINMAXPD xmm {k}{z}, xmm, m128/m64bcst, imm8 VMINMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512EVEX.128.66.0F3A.W1 52 /r ibAVX10.2
VMINMAXPD ymm {k}{z}, ymm, ymm, imm8 VMINMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512EVEX.256.66.0F3A.W1 52 /r ibAVX10.2
VMINMAXPD ymm {k}{z}, ymm, m256/m64bcst, imm8 VMINMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512EVEX.256.66.0F3A.W1 52 /r ibAVX10.2
VMINMAXPD zmm {k}{z}, zmm, zmm, imm8, {sae} VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512EVEX.512.66.0F3A.W1 52 /r ibAVX10.2
VMINMAXPD zmm {k}{z}, zmm, m512/m64bcst, imm8 VMINMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512EVEX.512.66.0F3A.W1 52 /r ibAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_minmax_pd __m128d _mm_minmax_pd(__m128d A, __m128d B, const int C)

VMINMAXPD xmm, xmm, xmm, imm8 EVEX.128 -mavx10.2

VMINMAXPD xmm, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2with AVX enabled

_mm_mask_minmax_pd __m128d _mm_mask_minmax_pd(__m128d W, __mmask8 U, __m128d A, __m128d B, const int C)

VMINMAXPD xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx10.2

VMINMAXPD xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2with AVX enabled

_mm_maskz_minmax_pd __m128d _mm_maskz_minmax_pd(__mmask8 U, __m128d A, __m128d B, const int C)

VMINMAXPD xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx10.2

VMINMAXPD xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2with AVX enabled

_mm256_minmax_pd __m256d _mm256_minmax_pd(__m256d A, __m256d B, const int C)

VMINMAXPD ymm, ymm, ymm, imm8 EVEX.256 -mavx10.2 -mavx

VMINMAXPD ymm, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2with AVX enabled

_mm256_mask_minmax_pd __m256d _mm256_mask_minmax_pd(__m256d W, __mmask8 U, __m256d A, __m256d B, const int C)

VMINMAXPD ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx10.2

VMINMAXPD ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2with AVX enabled

_mm256_maskz_minmax_pd __m256d _mm256_maskz_minmax_pd(__mmask8 U, __m256d A, __m256d B, const int C)

VMINMAXPD ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx10.2 -mavx

VMINMAXPD ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2with AVX enabled

_mm512_minmax_pd __m512d _mm512_minmax_pd(__m512d A, __m512d B, const int C)

VMINMAXPD zmm, zmm, zmm, imm8 EVEX.512 -mavx10.2 -mavx512f

VMINMAXPD zmm, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

_mm512_minmax_round_pd __m512d _mm512_minmax_round_pd(__m512d A, __m512d B, const int C, const int R)

VMINMAXPD zmm, zmm, zmm, imm8, {sae} EVEX.512 -mavx10.2 -mavx512f

VMINMAXPD zmm, zmm, zmm, imm8, {sae} EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

_mm512_mask_minmax_pd __m512d _mm512_mask_minmax_pd(__m512d W, __mmask8 U, __m512d A, __m512d B, const int C)

VMINMAXPD zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx10.2

VMINMAXPD zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_mask_minmax_round_pd __m512d _mm512_mask_minmax_round_pd(__m512d W, __mmask8 U, __m512d A, __m512d B, const int C, const int R)

VMINMAXPD zmm {k}, zmm, zmm, imm8, {sae} EVEX.512 -mavx10.2

VMINMAXPD zmm {k}, zmm, zmm, imm8, {sae} EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_maskz_minmax_pd __m512d _mm512_maskz_minmax_pd(__mmask8 U, __m512d A, __m512d B, const int C)

VMINMAXPD zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx10.2 -mavx512f

VMINMAXPD zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

_mm512_maskz_minmax_round_pd __m512d _mm512_maskz_minmax_round_pd(__mmask8 U, __m512d A, __m512d B, const int C, const int R)

VMINMAXPD zmm {k}{z}, zmm, zmm, imm8, {sae} EVEX.512 -mavx10.2 -mavx512f

VMINMAXPD zmm {k}{z}, zmm, zmm, imm8, {sae} EVEX.512 -mavx -mavx10.2 -mavx512fwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_MINMAX_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MINMAX_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MINMAX_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.