VMINMAXPH

VMINMAXPH applies one of the eight IEEE 754-2019 minimum and maximum operations to each pair of half-precision values in two vectors, 8, 16 or 32 pairs, with the immediate that VMINMAXPS’s page decodes. Its opcode is 52h in EVEX map 0F3A with no prefix and W0, where VMINMAXPS has 66; it takes a write mask, a broadcast half from memory, and {sae} on the 512-bit form. It belongs to AVX10.2, not AVX512-FP16, whose VMINPH and VMAXPH keep the older behavior of returning the second source for NaNs and equal zeros. VMINMAXSH handles one half.

Denormals#

The rules for NaNs, signed zeros and equal magnitudes are those on VMINMAXPD’s page. One thing differs: the AVX10.2 specification’s operation (revision 7.0) passes no DAZ setting for halves, so denormal halves compare at their value whatever MXCSR.DAZ says, as in the other half-precision arithmetic, while the single and double versions follow MXCSR.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 vectorizes a loop over _Float16 arrays computing __builtin_elementwise_minimum(p[i], q[i]) into VMINMAXPH with immediate 4 on zmm registers, the second source from memory. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = fminmax(a, b, imm8)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# imm8[1:0]: min, max, min |x|, max |x|; bit 4: a NaN yields; [3:2]: sign of a, own, 0, 1
# m16bcst: src3.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VDPPHPS
• VFMADD132BF16
• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS

All 96 AVX10.2 instructions