x86-64.net

Instruction

VMINMAXPH

Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed half-precision values, as an immediate selects, with sign control.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMINMAXPH that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMINMAXPH xmm {k}{z}, xmm, xmm, imm8 VMINMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512EVEX.128.NP.0F3A.W0 52 /r ibAVX10.2
VMINMAXPH xmm {k}{z}, xmm, m128/m16bcst, imm8 VMINMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512EVEX.128.NP.0F3A.W0 52 /r ibAVX10.2
VMINMAXPH ymm {k}{z}, ymm, ymm, imm8 VMINMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_IMM8_AVX512EVEX.256.NP.0F3A.W0 52 /r ibAVX10.2
VMINMAXPH ymm {k}{z}, ymm, m256/m16bcst, imm8 VMINMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_IMM8_AVX512EVEX.256.NP.0F3A.W0 52 /r ibAVX10.2
VMINMAXPH zmm {k}{z}, zmm, zmm, imm8, {sae} VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512EVEX.512.NP.0F3A.W0 52 /r ibAVX10.2
VMINMAXPH zmm {k}{z}, zmm, m512/m16bcst, imm8 VMINMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512EVEX.512.NP.0F3A.W0 52 /r ibAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_minmax_ph __m128h _mm_minmax_ph(__m128h A, __m128h B, const int C)

VMINMAXPH xmm, xmm, xmm, imm8 EVEX.128 -mavx10.2 -mavx512fp16

VMINMAXPH xmm, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm_mask_minmax_ph __m128h _mm_mask_minmax_ph(__m128h W, int U, __m128h A, __m128h B, const int C)

VMINMAXPH xmm, xmm, xmm, imm8 EVEX.128 -mavx10.2

VMINMAXPH xmm, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2with AVX enabled

_mm_maskz_minmax_ph __m128h _mm_maskz_minmax_ph(__mmask8 U, __m128h A, __m128h B, const int C)

VMINMAXPH xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx10.2 -mavx512fp16

VMINMAXPH xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm256_minmax_ph __m256h _mm256_minmax_ph(__m256h A, __m256h B, const int C)

VMINMAXPH ymm, ymm, ymm, imm8 EVEX.256 -mavx10.2 -mavx512fp16

VMINMAXPH ymm, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm256_mask_minmax_ph __m256h _mm256_mask_minmax_ph(__m256h W, __mmask16 U, __m256h A, __m256h B, const int C)

VMINMAXPH ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx10.2

VMINMAXPH ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2with AVX enabled

_mm256_maskz_minmax_ph __m256h _mm256_maskz_minmax_ph(__mmask16 U, __m256h A, __m256h B, const int C)

VMINMAXPH ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx10.2 -mavx512fp16

VMINMAXPH ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm512_minmax_ph __m512h _mm512_minmax_ph(__m512h A, __m512h B, const int C)

VMINMAXPH zmm, zmm, zmm, imm8 EVEX.512 -mavx10.2 -mavx512fp16

VMINMAXPH zmm, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm512_minmax_round_ph __m512h _mm512_minmax_round_ph(__m512h A, __m512h B, const int C, const int R)

VMINMAXPH zmm, zmm, zmm, imm8, {sae} EVEX.512 -mavx10.2 -mavx512fp16

VMINMAXPH zmm, zmm, zmm, imm8, {sae} EVEX.512 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm512_mask_minmax_ph __m512h _mm512_mask_minmax_ph(__m512h W, __mmask32 U, __m512h A, __m512h B, const int C)

VMINMAXPH zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx10.2

VMINMAXPH zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_mask_minmax_round_ph __m512h _mm512_mask_minmax_round_ph(__m512h W, __mmask32 U, __m512h A, __m512h B, const int C, const int R)

VMINMAXPH zmm {k}, zmm, zmm, imm8, {sae} EVEX.512 -mavx10.2

VMINMAXPH zmm {k}, zmm, zmm, imm8, {sae} EVEX.512 -mavx -mavx10.2with AVX enabled

_mm512_maskz_minmax_ph __m512h _mm512_maskz_minmax_ph(__mmask32 U, __m512h A, __m512h B, const int C)

VMINMAXPH zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx10.2 -mavx512fp16

VMINMAXPH zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx -mavx10.2 -mavx512fp16with AVX enabled

_mm512_maskz_minmax_round_ph __m512h _mm512_maskz_minmax_round_ph(__mmask32 U, __m512h A, __m512h B, const int C, const int R)

VMINMAXPH zmm {k}{z}, zmm, zmm, imm8, {sae} EVEX.512 -mavx10.2 -mavx512fp16

VMINMAXPH zmm {k}{z}, zmm, zmm, imm8, {sae} EVEX.512 -mavx -mavx10.2 -mavx512fp16with AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512_MINMAX_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MINMAX_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MINMAX_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.