Instruction
VMINMAXPS
Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of packed singles, as an immediate selects, with sign control.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
The classic MINPS and MAXPS, and their VEX and EVEX forms
VMINPS and VMAXPS, are not
symmetric: when either input is a NaN, or both are zeros of any sign,
they return the second source. Languages that need the IEEE 754-2019
operations, such as WebAssembly’s f32.min, therefore need several
extra instructions around them.
VMINMAXPS computes the standard operations directly. Its immediate selects one of eight:
| imm8[4] | imm8[1:0] | Operation |
|---|---|---|
| 0 | 00 / 01 | minimum / maximum: a NaN input gives a quiet NaN |
| 0 | 10 / 11 | minimumMagnitude / maximumMagnitude: compares absolute values |
| 1 | 00 / 01 | minimumNumber / maximumNumber: a NaN input loses to a number |
| 1 | 10 / 11 | minimumMagnitudeNumber / maximumMagnitudeNumber |
In all of them -0 is less than +0. Bits 3:2 control the sign of a non-NaN result: take the sign of the first source (00), keep the sign of the result (01), clear it (10) or set it (11). Bits 7:5 are reserved.
The same immediate works for VMINMAXPD, VMINMAXPH, VMINMAXBF16 and the scalar VMINMAXSS, VMINMAXSD and VMINMAXSH.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMINMAXPS xmm {k}{z}, xmm, xmm, imm8
VMINMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 | EVEX.128.66.0F3A.W0 52 /r ib | AVX10.2 |
VMINMAXPS xmm {k}{z}, xmm, m128/m32bcst, imm8
VMINMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 | EVEX.128.66.0F3A.W0 52 /r ib | AVX10.2 |
VMINMAXPS ymm {k}{z}, ymm, ymm, imm8
VMINMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 | EVEX.256.66.0F3A.W0 52 /r ib | AVX10.2 |
VMINMAXPS ymm {k}{z}, ymm, m256/m32bcst, imm8
VMINMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 | EVEX.256.66.0F3A.W0 52 /r ib | AVX10.2 |
VMINMAXPS zmm {k}{z}, zmm, zmm, imm8, {sae}
VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 | EVEX.512.66.0F3A.W0 52 /r ib | AVX10.2 |
VMINMAXPS zmm {k}{z}, zmm, m512/m32bcst, imm8
VMINMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 | EVEX.512.66.0F3A.W0 52 /r ib | AVX10.2 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMINMAXPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_minmax_ps
__m128 _mm_minmax_ps(__m128 A, __m128 B, const int C) |
|
_mm_mask_minmax_ps
__m128 _mm_mask_minmax_ps(__m128 W, __mmask8 U, __m128 A, __m128 B, const int C) |
|
_mm_maskz_minmax_ps
__m128 _mm_maskz_minmax_ps(__mmask8 U, __m128 A, __m128 B, const int C) |
|
_mm256_minmax_ps
__m256 _mm256_minmax_ps(__m256 A, __m256 B, const int C) |
|
_mm256_mask_minmax_ps
__m256 _mm256_mask_minmax_ps(__m256 W, __mmask8 U, __m256 A, __m256 B, const int C) |
|
_mm256_maskz_minmax_ps
__m256 _mm256_maskz_minmax_ps(__mmask8 U, __m256 A, __m256 B, const int C) |
|
_mm512_minmax_ps
__m512 _mm512_minmax_ps(__m512 A, __m512 B, const int C) |
|
_mm512_minmax_round_ps
__m512 _mm512_minmax_round_ps(__m512 A, __m512 B, const int C, const int R) |
|
_mm512_mask_minmax_ps
__m512 _mm512_mask_minmax_ps(__m512 W, __mmask16 U, __m512 A, __m512 B, const int C) |
|
_mm512_mask_minmax_round_ps
__m512 _mm512_mask_minmax_round_ps(__m512 W, __mmask16 U, __m512 A, __m512 B, const int C, const int R) |
|
_mm512_maskz_minmax_ps
__m512 _mm512_maskz_minmax_ps(__mmask16 U, __m512 A, __m512 B, const int C) |
|
_mm512_maskz_minmax_round_ps
__m512 _mm512_maskz_minmax_round_ps(__mmask16 U, __m512 A, __m512 B, const int C, const int R) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_MINMAX_128 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX512_MINMAX_256 | AVX10.2 | Nova Lake, Diamond Rapids |
AVX512_MINMAX_512 | AVX10.2 | Nova Lake, Diamond Rapids |
More AVX10.2 instructions
- VFMADD132BF16
- VFMADD213BF16
- VFMADD231BF16
- VFMSUB132BF16
- VFMSUB213BF16
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB132BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETEXPBF16
- VGETMANTBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXSD
- VMINMAXSH
- VMINMAXSS
- VMOVD
- VMOVW
- VMPSADBW
- VMULBF16
- VPDPBSSD
- VPDPBSSDS
- VPDPBSUD
- VPDPBSUDS
- VPDPBUUD
- VPDPBUUDS
- VPDPWSUD
- VPDPWSUDS
- VPDPWUSD
- VPDPWUSDS
- VPDPWUUD
- VPDPWUUDS
- VRCPBF16
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.