VMINMAXSD

VMINMAXSD applies one of the eight IEEE 754-2019 minimum and maximum operations to the low doubles of two sources, chosen by the immediate that VMINMAXPS’s page decodes, and copies bits 127:64 from the first source, as scalar instructions do. The second source may be eight bytes of memory. Its opcode is 53h in EVEX map 0F3A with a 66 prefix and W1, one above the packed VMINMAXPD’s 52h, whose page gives the rules for NaNs, signed zeros and equal magnitudes; the vector length is ignored, {sae} suppresses the exceptions, and a write mask decides through its lowest bit whether the result is written, zeroed or left as it was.

Against VMINSD#

VMINSD returns its second source whenever the inputs are unordered or both zeros, which is how C’s a < b ? a : b behaves, so compilers keep using it for that. VMINMAXSD gives the operations that newer languages define: immediate 4 is IEEE minimum, which propagates NaNs and puts -0 below +0, and 14h is minimumNumber, which ignores a single NaN. Both set bits 3:2 to 01b, keeping the sign of the result; with 00b, as in immediate 0, the result takes the first source’s sign, so a minimum of 3 and -2 comes out as +2.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles __builtin_elementwise_minimum(a, b) on two doubles to one VMINMAXSD with immediate 4 and __builtin_fmaximum_num(a, b) to one with immediate 15h; C’s fmin stays VMINSD, VCMPUNORDSD and a masked move. Clang prints the generic forms with only two registers, vminmaxsd xmm0, xmm1, 4, while the encoded instruction, read back with objdump, has all three, xmm0, xmm0, xmm1; _mm_minmax_sd prints all three. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = fminmax(a, b, imm8)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# imm8[1:0]: min, max, min |x|, max |x|; bit 4: a NaN yields; [3:2]: sign of a, own, 0, 1
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VFMADD213BF16
• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16

All 96 AVX10.2 instructions