VMINMAXSH

VMINMAXSH applies one of the eight IEEE 754-2019 minimum and maximum operations to the low half-precision values of two sources and copies bits 127:16 from the first. The immediate is the one that VMINMAXPS’s page decodes, and the rules for NaNs, signed zeros and equal magnitudes are on VMINMAXPD’s page. Its opcode is 53h in EVEX map 0F3A with no prefix and W0; the second source may be two bytes of memory, the vector length is ignored, and it takes a write mask on its one element and {sae}. Like VMINMAXPH, it compares denormal halves at their value whatever MXCSR.DAZ says.

Beside VMINSH#

AVX512-FP16’s VMINSH returns the second source when the inputs are unordered or both zeros, the behavior of VMINSD and its kin. VMINMAXSH gives the IEEE 754-2019 operations instead, with -0 below +0 and a choice between propagating NaNs and ignoring a single one; VMINMAXSD’s page lists the two immediates for them.

In our builds#

GCC 14 has no AVX10.2 option. Clang 23 with -mavx10.2 compiles __builtin_elementwise_minimum(a, b) on two _Float16 values to one VMINMAXSH with immediate 4. _mm_minmax_sh(a, b, 1), a maximum that takes the sign of a, becomes vminmaxsh xmm0, xmm0, xmm1, 1. No AVX10.2 processor appears in this site’s recorded cases.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = fminmax(a, b, imm8)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# imm8[1:0]: min, max, min |x|, max |x|; bit 4: a NaN yields; [3:2]: sign of a, own, 0, 1
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINMAXSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.2 instructions

• VFMADD231BF16
• VFMSUB132BF16
• VFMSUB213BF16
• VFMSUB231BF16
• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSS
• VMOVD
• VMOVW
• VMPSADBW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16

All 96 AVX10.2 instructions