Instruction
VMINMAXSS
Computes an IEEE 754-2019 minimum, maximum or magnitude comparison of the low singles, as an immediate selects, with sign control.
- Extensions
- Forms
- 2 (2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMINMAXSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_minmax_round_ss
__m128 _mm_minmax_round_ss(__m128 A, __m128 B, const int C, const int R) |
|
_mm_minmax_ss
__m128 _mm_minmax_ss(__m128 A, __m128 B, const int C) |
|
_mm_mask_minmax_round_ss
__m128 _mm_mask_minmax_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int C, const int R) |
|
_mm_mask_minmax_ss
__m128 _mm_mask_minmax_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int C) |
|
_mm_maskz_minmax_round_ss
__m128 _mm_maskz_minmax_round_ss(__mmask8 U, __m128 A, __m128 B, const int C, const int R) |
|
_mm_maskz_minmax_ss
__m128 _mm_maskz_minmax_ss(__mmask8 U, __m128 A, __m128 B, const int C) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_MINMAX_SCALAR | AVX10.2 | Nova Lake, Diamond Rapids |
More AVX10.2 instructions
- VFMSUB132BF16
- VFMSUB213BF16
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB132BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETEXPBF16
- VGETMANTBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXPS
- VMINMAXSD
- VMINMAXSH
- VMOVD
- VMOVW
- VMPSADBW
- VMULBF16
- VPDPBSSD
- VPDPBSSDS
- VPDPBSUD
- VPDPBSUDS
- VPDPBUUD
- VPDPBUUDS
- VPDPWSUD
- VPDPWSUDS
- VPDPWUSD
- VPDPWUSDS
- VPDPWUUD
- VPDPWUUDS
- VRCPBF16
- VREDUCEBF16
- VRNDSCALEBF16
- VRSQRTBF16
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.