VMINPD

VMINPD keeps the smaller double of each pair, by the rule of VMINPS: the first source comes back only when it is less than the second, and the second source otherwise. VMAXPD is the mirror image and shows that a quiet NaN alone sets IE; VMAXPS covers what the VEX and EVEX encodings add. AMD’s Zen 5 guide lists it with the same pipes and latency as VMAXPD.

Zeros and NaNs on Zen 5#

The rule shows best at its edges, in the cases recorded on Zen 5:

• vminpd ymm1, ymm2, ymm3 returned -0 for min(+0, -0) and +0 for min(-0, +0): with equal operands the second wins, whatever its sign.
• In vminpd ymm4, ymm4, ymmword ptr [mem], min(QNaN, 1) was 1 and min(1, QNaN) the NaN, and a signaling NaN as the second source came back unchanged, still signaling, with IE set.
• With DAZ set, the minimum of a positive denormal and a negative one was -0: both were read as zeros, and the second came back as a zero, not as the denormal it was.

Minimum of an array#

A loop such as m = b[i] < m ? b[i] : m is a reduction, and since VMINPD’s result depends on the order of its operands for NaNs and zeros, a compiler may only spread it over several elements when told that neither occurs. GCC 14 and Clang 23 at -O2 with -march=x86-64-v3 keep it a chain of scalar VMINSD by default, and also with only one of -ffinite-math-only and -fno-signed-zeros. With both, or with -ffast-math, they start from the initial value broadcast by VBROADCASTSD and take the minimum of four doubles per VMINPD (Clang keeps four such vectors), then fold the result with VEXTRACTF128, one more VMINPD on xmm registers and a last step on the two remaining elements, after VUNPCKHPD in GCC and VSHUFPD in Clang.

C’s fmin returns the number when only one argument is a NaN: GCC 14 calls the library for each element, and Clang 23 follows each VMINPD with a check of one source for NaN and VBLENDVPD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = fmin(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# a NaN or two zeros: b
# m64bcst: src3.f64[i] is the m64 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VDIVSS
• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD

All 253 AVX instructions

More AVX10.1 instructions

• VGETMANTSH
• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD

All 686 AVX10.1 instructions