VMINPH

VMINPH keeps the smaller half-precision value of each pair, 32 pairs in zmm registers, by the rule of VMINPS: the first source comes back only when it is less than the second, and the second source otherwise. So a NaN in either source, or two zeros of any sign, give the second source as it is, a signaling NaN included, which is not made quiet. VADDPH covers the FP16 format, the CPUID bits and the encoding in EVEX map 5, where VMINPH has opcode 5Dh, that of MINPS; VMAXPH is the mirror image and VMINSH the scalar form.

What halves change#

The result is always one of the inputs, so nothing is rounded: the instruction takes no rounding mode, only {sae} on the 512-bit register form. Intel’s optimization manual says that FP16 instructions ignore MXCSR.DAZ (Section 18.5.4). Where VMINPS with DAZ set reads a denormal as a zero and returns that zero, VMINPH compares the denormal itself and can return it. Intel’s entry still lists the denormal exception, with invalid, among those VMINPH reports.

The same manual suggests an integer shortcut (Section 18.6.3): two halves that are not NaNs, and are both positive or of opposite signs, order like their bit patterns read as signed words, so VPMINSW gives their minimum with one cycle of latency, though with less throughput than VMINPH. Zeros are the exception: for -0 against +0, VPMINSW returns -0, whose pattern 8000h is the smallest word, where VMINPH returns the second source.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 and Clang 23 compile c[i] = a[i] < b[i] ? a[i] : b[i] over _Float16 arrays to VMINPH with b[i] read from memory, GCC on zmm registers and Clang on ymm registers. Without AVX512-FP16, as with -march=znver5, GCC widens each pair with VCVTPH2PS, compares with VCOMISS and branches. Clang widens sixteen halves at a time, compares the singles into mask registers with VCMPPS, joins two masks with KUNPCKWD and picks the original halves with a masked VMOVDQU16: the answer is an input, so nothing needs narrowing back.

AMD’s Zen 5 guide does not list AVX512-FP16 among Zen 5’s AVX-512 extensions, and this site’s recorded cases include none of VMINPH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        a = zmm2.f16[i]
        b = src3.f16[i]
        zmm1.f16[i] = fmin(a, b)
    elif zeroing:
        zmm1.f16[i] = 0
    # else: zmm1.f16[i] keeps its value
# a NaN or two zeros: b
# m16bcst: src3.f16[i] is the m16 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINPH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGETMANTSS
• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS

All 686 AVX10.1 instructions