VMINPS

VMINPS is MINPS in VEX and EVEX encodings, with the same asymmetric rule: it returns the first source only when that is less than the second, and the second source otherwise. VMAXPS is its mirror and covers what the encodings add, including {sae}. Zen 5’s recorded cases show the rule at its edges:

• min(1, QNaN) was the QNaN, min(SNaN, 1) was 1: a NaN in the first source is lost, as in VMAXPS.
• min(QNaN, SNaN) returned the signaling NaN unchanged, not quieted, and set IE; so did a signaling NaN broadcast from memory as the second source.
• With DAZ set, the minimum of a negative denormal and itself was -0: the input is read as a zero of its sign, and that zero is what comes back, not the denormal.

Clamping#

A clamp, x = x < 0.0f ? 0.0f : x; x = x > 1.0f ? 1.0f : x;, has two such comparisons, and the order of the operands decides what a NaN gives. Clang 23 at -O2 with -march=x86-64-v3 vectorizes a loop of it into a VMAXPS with the zero as the first source and the element as the second, then a VMINPS with 1 first: a NaN element is the second source both times and comes out as a NaN, as the C code says it must. GCC 14 leaves the same loop scalar, with a VCOMISS and a branch for the lower bound and a VMINSS for the upper one. Where C’s fminf and fmaxf are wanted instead, the result differs: they return the number and drop the NaN, which takes more than VMINPS (see the MINPS page).

AMD’s Zen 5 guide runs VMINPS, like VMAXPS and the additions, on pipes FP2 and FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f32[i]
        b = src3.f32[i]
        zmm1.f32[i] = fmin(a, b)
    elif zeroing:
        zmm1.f32[i] = 0
    # else: zmm1.f32[i] keeps its value
# a NaN or two zeros: b
# m32bcst: src3.f32[i] is the m32 for every i
# {sae}: no exception flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VDPPD
• VDPPS
• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS

All 253 AVX instructions

More AVX10.1 instructions

• VGF2P8AFFINEINVQB
• VGF2P8AFFINEQB
• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ

All 686 AVX10.1 instructions