VMINSD instruction (AVX, AVX10.1)

VMINSD is MINSD in VEX and EVEX encodings: the smaller of the low doubles of its two sources, with the high double copied from the first source and the bits above 127 cleared. The first source comes back only when it is less than the second, so a NaN in either, or two zeros, give the second; MINSD’s page shows what that means for std::min and fmin. VMAXSD covers what the encodings add: AVX for VEX, AVX-512F or AVX10.1 for EVEX with a write mask on the low double and {sae}, and no wider form. Zen 5’s recorded cases:

vminsd xmm4, xmm4, xmm4, under MXCSR 3FC0H, compared the quiet NaN FFF8000000000000H with itself, returned it and set IE: the minimum reports even a quiet NaN as invalid.
vminsd xmm1, xmm2, qword ptr [mem], under 7F80H, returned 0 from memory against 1.0 and copied the high double of XMM2, -1.0.
vminsd xmm17{k4}, xmm30, xmm2, {sae}, with bit 0 of K4 set, gave -2^-53 from XMM2 against 1.0, and +infinity, the high double of XMM30, above it.

Clamping a double

x = x < 0.0 ? 0.0 : x; x = x > 1.0 ? 1.0 : x; shows the two compilers apart. In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, Clang 23 compiles it on one double to VMAXSD with the zero as first source and VMINSD with 1.0 as first source, no branch, and a loop doing it over a global array to VMAXPD and VMINPD on ymm registers. GCC 14 tests the lower bound with VCOMISD and a branch before vminsd xmm0, xmm1, xmm0, and leaves the loop scalar with that branch inside. The running minimum of an array is a VMOVSD load and vminsd xmm0, xmm2, xmm1 in GCC, followed by a VMOVAPD that copies the result back each iteration; Clang computes into the register that holds the minimum.

AMD’s latency spreadsheet for Zen 5 lists the VEX and the EVEX rows at 2 cycles on pipes FP2 and FP3, two per cycle, like VMAXSD.

Forms

Every encoding of VMINSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMINSD xmm, xmm, m64` VMINSD_XMMdq_XMMdq_MEMq	`VEX.LIG.F2.0F.WIG 5D /r`	AVX
`VMINSD xmm, xmm, xmm` VMINSD_XMMdq_XMMdq_XMMq	`VEX.LIG.F2.0F.WIG 5D /r`	AVX
`VMINSD xmm {k}{z}, xmm, xmm, {sae}` VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512	`EVEX.LIG.F2.0F.W1 5D /r`	AVX10.1 or AVX512F
`VMINSD xmm {k}{z}, xmm, m64` VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512	`EVEX.LIG.F2.0F.W1 5D /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m64` `xmm {k}{z}, xmm, m64`	`xmm, xmm, xmm` `xmm {k}{z}, xmm, xmm, {sae}`no mask, with a mask, zeroing	`xmm {k}{z}, xmm, xmm, {sae}`with {sae}
Sandy Bridge	9 / 1p1	3 / 1p1
Haswell, Broadwell	8 / 1p1	3 / 1p1
Skylake	9 / 0.5p01	4 / 0.5p01
Skylake-SP, Ice Lake	9 / 0.5p01	4 / 0.5p01	4 / 0.5p01
Alder Lake	11 / 0.5p01	4 / 0.5p01
Sapphire Rapids	11 / 0.5p01	4 / 0.5p01	4 / 0.5p01
Lunar Lake	10 / 2V0 V1	4 / 2V0 V1
Piledriver	7 / 1.5FPFMA FPU0	2 / 1FPFMA FPU0
Zen, Zen 2	8 / 0.5FPU0 FPU1	1 / 0.5FPU0 FPU1
Zen 3	8 / 0.5FP0 FP1	1 / 0.5FP0 FP1
Zen 4	8 / 0.5FP0 FP1	2 / 1¹FP0 FP1	1 / 0.5²FP0 FP1
Jaguar	7 / 1FPA FPU0	2 / 1FPA FPU0

Zen 4 model: AMD's spreadsheets give reciprocal throughput 0.5 for Zen 4 and Zen 5 (AMD 57647, row 1572; AMD 58455, row 1090).
Zen 4 model: AMD's spreadsheets give latency 2 for Zen 4 and Zen 5 (AMD 57647, row 1573; AMD 58455, row 133).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm2.

The write mask k1 applies to the low double: with bit 0 clear it keeps its old value, or is zeroed with {z}.

Result double 0 is computed from double 0 of xmm2 and xmm3; double 1 is that of xmm2. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f64[0]
    b = src3.f64[0]
    xmm1.f64[0] = fmin(a, b)
elif zeroing:
    xmm1.f64[0] = 0
# else: xmm1.f64[0] keeps its value
xmm1.q[1] = xmm2.q[1]
# {sae}: no exception flags
# a NaN or two zeros: b
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMINSD xmm, xmm, xmm/m64`
`xmm`	explicit	write
`xmm`	explicit	read
`xmm/m64`	explicit	read
`VMINSD xmm {k}{z}, xmm, xmm/m64, {sae}`
`xmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`xmm`	explicit	read
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-3
EVEX forms: AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
EVEX forms: write masking
EVEX memory forms: memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_min_round_sd` `__m128d _mm_min_round_sd(__m128d A, __m128d B, const int R)`	`VMINSD xmm, xmm, xmm, {sae}` EVEX.LIG -mavx512f
`_mm_min_sd` `__m128d _mm_min_sd(__m128d __a, __m128d __b)`	`VMINSD xmm, xmm, xmm` VEX.LIG -mavxwith AVX enabled
`_mm_mask_min_round_sd` `__m128d _mm_mask_min_round_sd(__m128d W, __mmask8 U, __m128d A, __m128d B, const int R)`	`VMINSD xmm {k}, xmm, xmm, {sae}` EVEX.LIG -mavx512f
`_mm_mask_min_sd` `__m128d _mm_mask_min_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)`	`VMINSD xmm {k}, xmm, xmm` EVEX.LIG -mavx512f
`_mm_maskz_min_round_sd` `__m128d _mm_maskz_min_round_sd(__mmask8 U, __m128d A, __m128d B, const int R)`	`VMINSD xmm {k}{z}, xmm, xmm, {sae}` EVEX.LIG -mavx512f
`_mm_maskz_min_sd` `__m128d _mm_maskz_min_sd(__mmask8 __U, __m128d __A, __m128d __B)`	`VMINSD xmm {k}{z}, xmm, xmm` EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_SCALAR` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_SCALAR

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Clamping a double#