VMINSH

VMINSH is the scalar form of VMINPH: the smaller of the low halves of its two sources, with the first source returned only when it is less than the second, so a NaN in either, or two zeros, give the second. Bits 127:16 come from the first source and the bits above 127 are cleared, as VMINSS does for singles. It is EVEX-only, opcode 5Dh with the F3 prefix in map 5, takes a write mask on the low half and {sae}, and reads two bytes when its second source is in memory. VADDPH covers the format and the CPUID bits; VMAXSH is the maximum.

fminf16#

C’s fminf16 must return the number when only one argument is a NaN, which the rule does only for a NaN first source. At -O2 with -march=x86-64-v4 -mavx512fp16, GCC 14 calls the library function. Clang 23 computes VMINSH with the arguments swapped, tests the first argument with VCMPSH’s unordered predicate into a mask register and, where it is a NaN, takes the second argument with a masked VMOVSH, the FP16 version of the fix-up that VMAXSS’s page shows for fmaxf. x < y ? x : y is a plain vminsh xmm0, xmm0, xmm1 in both compilers.

Minimum of an array#

m = a[i] < m ? a[i] : m over a _Float16 array keeps a chain of VMINSH in both compilers, since the element must be the first source and so cannot be read from memory in place: GCC loads each half with VMOVW and copies the result back with a VMOVAPS each iteration, while Clang loads with VMOVSH and computes into the register that holds the minimum, unrolled eight times. Intel’s optimization manual lists _mm512_reduce_min_ph among the convenience intrinsics that reduce a vector in steps (Section 18.6.2), the route that VMAXPH’s page follows for the maximum.

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VMINSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    a = xmm2.f16[0]
    b = src3.f16[0]
    xmm1.f16[0] = fmin(a, b)
elif zeroing:
    xmm1.f16[0] = 0
# else: xmm1.f16[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# {sae}: no exception flags
# a NaN or two zeros: b
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

write masking; follows MXCSR

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VGF2P8MULB
• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD

All 686 AVX10.1 instructions