Instruction
VMINSS
Returns the smaller of the low singles, or the second operand if either is NaN or both are zero; the other elements come from the first source.
- Extensions
- Forms
- 4 (2 VEX, 2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMINSS xmm, xmm, m32
VMINSS_XMMdq_XMMdq_MEMd | VEX.LIG.F3.0F.WIG 5D /r | AVX |
VMINSS xmm, xmm, xmm
VMINSS_XMMdq_XMMdq_XMMd | VEX.LIG.F3.0F.WIG 5D /r | AVX |
VMINSS xmm {k}{z}, xmm, xmm, {sae}
VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | EVEX.LIG.F3.0F.W0 5D /r | AVX10.1 or AVX512F |
VMINSS xmm {k}{z}, xmm, m32
VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 | EVEX.LIG.F3.0F.W0 5D /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMINSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_min_round_ss
__m128 _mm_min_round_ss(__m128 A, __m128 B, const int R) |
|
_mm_min_ss
__m128 _mm_min_ss(__m128 __a, __m128 __b) |
|
_mm_mask_min_round_ss
__m128 _mm_mask_min_round_ss(__m128 W, __mmask8 U, __m128 A, __m128 B, const int R) |
|
_mm_mask_min_ss
__m128 _mm_mask_min_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) |
|
_mm_maskz_min_round_ss
__m128 _mm_maskz_min_round_ss(__mmask8 U, __m128 A, __m128 B, const int R) |
|
_mm_maskz_min_ss
__m128 _mm_maskz_min_ss(__mmask8 __U, __m128 __A, __m128 __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_SCALAR | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
- VINSERTF32X4
- VINSERTF32X8
- VINSERTF64X2
- VINSERTF64X4
- VINSERTI32X4
- VINSERTI32X8
- VINSERTI64X2
- VINSERTI64X4
- VINSERTPS
- VMAXPD
- VMAXPH
- VMAXPS
- VMAXSD
- VMAXSH
- VMAXSS
- VMINPD
- VMINPH
- VMINPS
- VMINSD
- VMINSH
- VMOVAPD
- VMOVAPS
- VMOVD
- VMOVDDUP
- VMOVDQA32
- VMOVDQA64
- VMOVDQU16
- VMOVDQU32
- VMOVDQU64
- VMOVDQU8
- VMOVHLPS
- VMOVHPD
- VMOVHPS
- VMOVLHPS
- VMOVLPD
- VMOVLPS
- VMOVNTDQ
- VMOVNTDQA
- VMOVNTPD
- VMOVNTPS
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.