VMINSS

VMINSS is MINSS in VEX and EVEX encodings: the smaller of the low singles of its two sources, with singles 1 to 3 copied from the first source and the bits above 127 cleared. It returns the first source only when that is less than the second, so a NaN in either, or two zeros, give the second. VMAXSS covers what the encodings add and why the operand order decides where a memory operand can go. Zen 5’s recorded cases:

• vminss xmm7, xmm11, xmm7, under MXCSR 3FC0H, compared the quiet NaNs 7FC00000H and FFC00000H, returned the second and set IE. Unlike an addition, the minimum reports a quiet NaN as an invalid operation, as Intel’s entry for MINSS lists.
• vminss xmm1{k3}{z}, xmm2, dword ptr [mem], with bit 0 of K3 set and MXCSR at FFC0H, compared the signaling NaN 7F812345H with 1 and returned 1, setting IE: the NaN is lost. The upper singles of XMM2, two of them denormals, were copied unchanged, although FTZ and DAZ were set.

Clamping a float#

x = x < 0.0f ? 0.0f : x; x = x > 1.0f ? 1.0f : x; on one float compiles as the loop on VMINPS’s page does. In our builds with -march=x86-64-v3 or x86-64-v4, Clang 23 emits VMAXSS with the zero as first source and then VMINSS with 1 as first source, so a NaN in x is the second source both times and comes out as a NaN. GCC 14 tests the lower bound with VCOMISS and a branch, then emits vminss xmm0, xmm1, xmm0 with 1 in XMM1. fminf follows fmaxf on VMAXSS’s page: a library call in GCC, VMINSS with a NaN fix-up in Clang.

AMD’s latency spreadsheet for Zen 5 lists it at 2 cycles on pipes FP2 and FP3, like VMAXSS.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    a = xmm2.f32[0]
    b = src3.f32[0]
    xmm1.f32[0] = fmin(a, b)
elif zeroing:
    xmm1.f32[0] = 0
# else: xmm1.f32[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# {sae}: no exception flags
# a NaN or two zeros: b
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-3

EVEX forms

AVX512-E3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMINSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VEXTRACTF128
• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD

All 253 AVX instructions

More AVX10.1 instructions

• VINSERTF32X4
• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS

All 686 AVX10.1 instructions