Instruction
VMLAUNCH
Enters the guest that the current VMCS describes, for a VMCS whose launch state is clear, and marks the VMCS launched.
- Extensions
- Forms
- 1 (1 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMLAUNCH
VMLAUNCH | NP 0F 01 C2 | VMX |
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
if not in_vmx:
fault(UD)
if vmx_nonroot:
vm_exit(20) # the hypervisor emulates it
if CPL > 0:
fault(GP, 0)
p = current_vmcs
if p == NO_VMCS:
vm_fail_invalid()
elif phys_read(p, 32) >> 31:
vm_fail_invalid() # a shadow VMCS: no VM entry
elif mov_ss:
vm_fail(26) # right after MOV SS or POP SS
elif launched(p):
vm_fail(4) # VMRESUME enters it again
elif not controls_ok():
vm_fail(7) # 29.2.1, in an order of the
# processor's: a VMCS that fails
# both may give either number
elif not host_state_ok():
vm_fail(8) # 29.2.2 and 29.2.3
elif not guest_state_ok():
entry_fail(33) # 29.3.1: back to the host
else:
load_guest() # 29.3.2; address monitoring
# cleared
if not msr_load_ok():
entry_fail(34) # 29.4: back to the host
else:
set_launched(p)
vmx_nonroot = 1 # the guest runs from its RIP, an
# event injected first if the
# VM-entry controls ask (29.6)
Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no VMX, and every one raised an exception.
Operands
| Operand | Kind | Action |
|---|---|---|
VMLAUNCH | ||
RFLAGS | implicit | read, conditional write |
Flags
| When | OF | SF | ZF | AF | PF | CF | DF | IF | TF | AC | IOPL | NT | RF | VM | VIF | VIP | ID |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| All forms | |||||||||||||||||
| in some cases | M | M | M | M | M | M | M | M | M | M | TM | M | M | T | M | M | M |
Attributes
What else XED records about the forms. How to read.
- All forms
- privileged: CPL 0 only; may abort a TSX transaction
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
VTX | VMX | Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill Note: XED's AMD chips, which it derives from its Intel chips, have VMX too; AMD processors implement AMD-V (SVM) instead, so this list leaves them out. |
More VMX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3C, page 33-14 (VMLAUNCH/
VMRESUME)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.