x86-64.net

Instruction

VMMCALL

Exits from a guest to its hypervisor with a VM exit, for a call whose meaning the hypervisor defines; AMD SVM.

AMD's virtualization extension: Intel processors implement VMX instead.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMMCALL that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMMCALL VMMCALL0F 01 D9SVM

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not efer >> 12 & 1:
    fault(UD)                    # EFER.SVME clear: SVM off
if intercepted(0x81):
    vm_exit(0x81)                # the hypercall, at any CPL: what
                                 # it means is the hypervisor's
fault(UD)                        # not intercepted: no call

Not run on a processor: the probe never runs VMMCALL: in a KVM guest it is a hypercall, which KVM answers at CPL 3 with an error in RAX rather than a fault.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SVM

SVM
CPUID.80000001H:ECX[2] SVM

K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More SVM instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.36, March 2024), Wayback Machine copy of AMD's PDF
  4. AMD64 Architecture Programmer's Manual, Volume 2: System Programming (24593, rev. 3.42, March 2024), Wayback Machine copy of AMD's PDF

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.