VMOVAPD

VMOVAPD is MOVAPD in VEX and EVEX encodings, and the double-precision twin of VMOVAPS: a copy of 16, 32 or 64 bytes between vector registers, or between a register and memory aligned to that size, bits not interpreted. The VMOVAPS page covers what the two share: the alignment fault, which a write mask does not relax, and the clearing of the register above the vector width. What the PD name changes:

• A mask bit per double. In the EVEX forms (AVX512F, or AVX10.1) each bit of the write mask selects a quadword. On Zen 5, vmovapd zmmword ptr [mem]{k2}, zmm9 with C9h in the low byte of K2 wrote doubles 0, 3, 6 and 7 and left the other four in memory as they were. VMOVDQA64 is the same masked move under an integer name.
• No longer than VMOVAPS. Legacy MOVAPD needs a 66 prefix that MOVAPS does without; VEX and EVEX encode it in a field of their own, so the PD and PS forms have the same length.

In compiled code#

Without a mask the choice is the compiler’s taste. At -O2 with -march=x86-64-v3 or -v4, GCC 14 names the move after the data: VMOVAPD for _mm256_load_pd and _mm256_store_pd, and for a loop over double arrays declared aligned with __builtin_assume_aligned, on zmm registers with -v4. Clang 23 compiles the two intrinsics to VMOVAPS but the loop to VMOVAPD on ymm registers. Where a mask makes the element size matter, both emit VMOVAPD: for _mm512_maskz_load_pd, _mm512_mask_store_pd and _mm512_mask_blend_pd, the last as vmovapd zmm0{k1}, zmm1. Without the alignment hint, the loop uses VMOVUPD.

AMD’s Zen 5 guide names VMOVAPD in its advice to load and store whole registers rather than halves, as MOVLPD and MOVHPD would (Section 2.11.2). Zen 5’s 17 recorded cases cover every form, the masked loads and stores included, all at an aligned address.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        mem.q[i] = zmm2.q[i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-1

EVEX forms

AVX512-E1

Attributes

What else XED records about the forms. How to read.

Memory forms

aligned memory operand

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVAPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VEXTRACTPS
• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP

All 253 AVX instructions

More AVX10.1 instructions

• VINSERTF32X8
• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ

All 686 AVX10.1 instructions