x86-64.net

Instruction

VMOVAPD

Moves packed doubles between registers and memory that must be aligned to the vector size.

Extensions
Forms
17 (8 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVAPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVAPD xmm, m128 VMOVAPD_XMMdq_MEMdqVEX.128.66.0F.WIG 28 /rAVX
VMOVAPD xmm, xmm VMOVAPD_XMMdq_XMMdq_28VEX.128.66.0F.WIG 28 /rAVX
VMOVAPD m128, xmm VMOVAPD_MEMdq_XMMdqVEX.128.66.0F.WIG 29 /rAVX
VMOVAPD xmm, xmm VMOVAPD_XMMdq_XMMdq_29VEX.128.66.0F.WIG 29 /rAVX
VMOVAPD ymm, m256 VMOVAPD_YMMqq_MEMqqVEX.256.66.0F.WIG 28 /rAVX
VMOVAPD ymm, ymm VMOVAPD_YMMqq_YMMqq_28VEX.256.66.0F.WIG 28 /rAVX
VMOVAPD m256, ymm VMOVAPD_MEMqq_YMMqqVEX.256.66.0F.WIG 29 /rAVX
VMOVAPD ymm, ymm VMOVAPD_YMMqq_YMMqq_29VEX.256.66.0F.WIG 29 /rAVX
VMOVAPD zmm {k}{z}, zmm VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512EVEX.512.66.0F.W1 28 /r
EVEX.512.66.0F.W1 29 /r		AVX10.1 or AVX512F
VMOVAPD zmm {k}{z}, m512 VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512EVEX.512.66.0F.W1 28 /rAVX10.1 or AVX512F
VMOVAPD m512 {k}, zmm VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512EVEX.512.66.0F.W1 29 /rAVX10.1 or AVX512F
VMOVAPD xmm {k}{z}, xmm VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512EVEX.128.66.0F.W1 28 /r
EVEX.128.66.0F.W1 29 /r		AVX10.1 or AVX512F + AVX512VL
VMOVAPD xmm {k}{z}, m128 VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512EVEX.128.66.0F.W1 28 /rAVX10.1 or AVX512F + AVX512VL
VMOVAPD m128 {k}, xmm VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512EVEX.128.66.0F.W1 29 /rAVX10.1 or AVX512F + AVX512VL
VMOVAPD ymm {k}{z}, ymm VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512EVEX.256.66.0F.W1 28 /r
EVEX.256.66.0F.W1 29 /r		AVX10.1 or AVX512F + AVX512VL
VMOVAPD ymm {k}{z}, m256 VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512EVEX.256.66.0F.W1 28 /rAVX10.1 or AVX512F + AVX512VL
VMOVAPD m256 {k}, ymm VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512EVEX.256.66.0F.W1 29 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVAPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_load_pd __m128d _mm_load_pd(const double *__dp)

VMOVAPD xmm, m128 VEX.128 -mavxwith AVX enabled

_mm_store_pd void _mm_store_pd(double *__dp, __m128d __a)

VMOVAPD m128, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_blend_pd __m128d _mm_mask_blend_pd(__mmask8 __U, __m128d __A, __m128d __W)

VMOVAPD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_load_pd __m128d _mm_mask_load_pd(__m128d __W, __mmask8 __U, const void *__P)

VMOVAPD xmm {k}, m128 EVEX.128 -mavx512vl

_mm_mask_mov_pd __m128d _mm_mask_mov_pd(__m128d __W, __mmask8 __U, __m128d __A)

VMOVAPD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_permute_pd __m128d _mm_mask_permute_pd(__m128d W, __mmask8 U, __m128d X, const int C)

VMOVAPD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_store_pd void _mm_mask_store_pd(void *__P, __mmask8 __U, __m128d __A)

VMOVAPD m128 {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_load_pd __m128d _mm_maskz_load_pd(__mmask8 __U, const void *__P)

VMOVAPD xmm {k}{z}, m128 EVEX.128 -mavx512vl

_mm_maskz_mov_pd __m128d _mm_maskz_mov_pd(__mmask8 __U, __m128d __A)

VMOVAPD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm_maskz_permute_pd __m128d _mm_maskz_permute_pd(__mmask8 U, __m128d X, const int C)

VMOVAPD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_load_pd __m256d _mm256_load_pd(const double *__p)

VMOVAPD ymm, m256 VEX.256 -mavx

_mm256_store_pd void _mm256_store_pd(double *__p, __m256d __a)

VMOVAPD m256, ymm VEX.256 -mavx

_mm256_mask_blend_pd __m256d _mm256_mask_blend_pd(__mmask8 __U, __m256d __A, __m256d __W)

VMOVAPD ymm {k}, ymm EVEX.256 -mavx512vl

_mm256_mask_load_pd __m256d _mm256_mask_load_pd(__m256d __W, __mmask8 __U, const void *__P)

VMOVAPD ymm {k}, m256 EVEX.256 -mavx512vl

_mm256_mask_mov_pd __m256d _mm256_mask_mov_pd(__m256d __W, __mmask8 __U, __m256d __A)

VMOVAPD ymm {k}, ymm EVEX.256 -mavx512vl

_mm256_mask_store_pd void _mm256_mask_store_pd(void *__P, __mmask8 __U, __m256d __A)

VMOVAPD m256 {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_load_pd __m256d _mm256_maskz_load_pd(__mmask8 __U, const void *__P)

VMOVAPD ymm {k}{z}, m256 EVEX.256 -mavx512vl

_mm256_maskz_mov_pd __m256d _mm256_maskz_mov_pd(__mmask8 __U, __m256d __A)

VMOVAPD ymm {k}{z}, ymm EVEX.256 -mavx512vl

_mm512_load_pd __m512d _mm512_load_pd(const void *__p)

VMOVAPD zmm, m512 EVEX.512 -mavx512f

_mm512_store_pd void _mm512_store_pd(void *__P, __m512d __A)

VMOVAPD m512, zmm EVEX.512 -mavx512f

_mm512_mask_blend_pd __m512d _mm512_mask_blend_pd(__mmask8 __U, __m512d __A, __m512d __W)

VMOVAPD zmm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_load_pd __m512d _mm512_mask_load_pd(__m512d __W, __mmask8 __U, const void *__P)

VMOVAPD zmm {k}, m512 EVEX.512 -mavx512f

_mm512_mask_mov_pd __m512d _mm512_mask_mov_pd(__m512d __W, __mmask8 __U, __m512d __A)

VMOVAPD zmm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_store_pd void _mm512_mask_store_pd(void *__P, __mmask8 __U, __m512d __A)

VMOVAPD m512 {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_load_pd __m512d _mm512_maskz_load_pd(__mmask8 __U, const void *__P)

VMOVAPD zmm {k}{z}, m512 EVEX.512 -mavx512f

_mm512_maskz_mov_pd __m512d _mm512_maskz_mov_pd(__mmask8 __U, __m512d __A)

VMOVAPD zmm {k}{z}, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.