x86-64.net

Instruction

VMOVAPS

Moves packed singles between registers and memory that must be aligned to the vector size.

Extensions
Forms
17 (8 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVAPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVAPS xmm, m128 VMOVAPS_XMMdq_MEMdqVEX.128.NP.0F.WIG 28 /rAVX
VMOVAPS xmm, xmm VMOVAPS_XMMdq_XMMdq_28VEX.128.NP.0F.WIG 28 /rAVX
VMOVAPS m128, xmm VMOVAPS_MEMdq_XMMdqVEX.128.NP.0F.WIG 29 /rAVX
VMOVAPS xmm, xmm VMOVAPS_XMMdq_XMMdq_29VEX.128.NP.0F.WIG 29 /rAVX
VMOVAPS ymm, m256 VMOVAPS_YMMqq_MEMqqVEX.256.NP.0F.WIG 28 /rAVX
VMOVAPS ymm, ymm VMOVAPS_YMMqq_YMMqq_28VEX.256.NP.0F.WIG 28 /rAVX
VMOVAPS m256, ymm VMOVAPS_MEMqq_YMMqqVEX.256.NP.0F.WIG 29 /rAVX
VMOVAPS ymm, ymm VMOVAPS_YMMqq_YMMqq_29VEX.256.NP.0F.WIG 29 /rAVX
VMOVAPS zmm {k}{z}, zmm VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512EVEX.512.NP.0F.W0 28 /r
EVEX.512.NP.0F.W0 29 /r		AVX10.1 or AVX512F
VMOVAPS zmm {k}{z}, m512 VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512EVEX.512.NP.0F.W0 28 /rAVX10.1 or AVX512F
VMOVAPS m512 {k}, zmm VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512EVEX.512.NP.0F.W0 29 /rAVX10.1 or AVX512F
VMOVAPS xmm {k}{z}, xmm VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512EVEX.128.NP.0F.W0 28 /r
EVEX.128.NP.0F.W0 29 /r		AVX10.1 or AVX512F + AVX512VL
VMOVAPS xmm {k}{z}, m128 VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512EVEX.128.NP.0F.W0 28 /rAVX10.1 or AVX512F + AVX512VL
VMOVAPS m128 {k}, xmm VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512EVEX.128.NP.0F.W0 29 /rAVX10.1 or AVX512F + AVX512VL
VMOVAPS ymm {k}{z}, ymm VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512EVEX.256.NP.0F.W0 28 /r
EVEX.256.NP.0F.W0 29 /r		AVX10.1 or AVX512F + AVX512VL
VMOVAPS ymm {k}{z}, m256 VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512EVEX.256.NP.0F.W0 28 /rAVX10.1 or AVX512F + AVX512VL
VMOVAPS m256 {k}, ymm VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512EVEX.256.NP.0F.W0 29 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVAPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_load_pbh __m128bh _mm_load_pbh(const void *__p)

VMOVAPS xmm, m128 VEX.128 -mavx10.2

_mm_load_ph __m128h _mm_load_ph(const void *__p)

VMOVAPS xmm, m128 VEX.128 -mavx512fp16

_mm_load_ps __m128 _mm_load_ps(const float *__p)

VMOVAPS xmm, m128 VEX.128 -mavxwith AVX enabled

_mm_store_pbh void _mm_store_pbh(void *__P, __m128bh __A)

VMOVAPS m128, xmm VEX.128 -mavx10.2

_mm_store_ph void _mm_store_ph(void *__P, __m128h __A)

VMOVAPS m128, xmm VEX.128 -mavx512fp16

_mm_store_ps void _mm_store_ps(float *__p, __m128 __a)

VMOVAPS m128, xmm VEX.128 -mavxwith AVX enabled

_mm_store_si128 void _mm_store_si128(__m128i *__p, __m128i __b)

VMOVAPS m128, xmm VEX.128 -mavxwith AVX enabled; Clang emits the equivalent VMOVDQA

_mm_mask_blend_ps __m128 _mm_mask_blend_ps(__mmask8 __U, __m128 __A, __m128 __W)

VMOVAPS xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_load_ps __m128 _mm_mask_load_ps(__m128 __W, __mmask8 __U, const void *__P)

VMOVAPS xmm {k}, m128 EVEX.128 -mavx512vl

_mm_mask_mov_ps __m128 _mm_mask_mov_ps(__m128 __W, __mmask8 __U, __m128 __A)

VMOVAPS xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_store_ps void _mm_mask_store_ps(void *__P, __mmask8 __U, __m128 __A)

VMOVAPS m128 {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_load_ps __m128 _mm_maskz_load_ps(__mmask8 __U, const void *__P)

VMOVAPS xmm {k}{z}, m128 EVEX.128 -mavx512vl

_mm_maskz_mov_ps __m128 _mm_maskz_mov_ps(__mmask8 __U, __m128 __A)

VMOVAPS xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_load_pbh __m256bh _mm256_load_pbh(const void *__p)

VMOVAPS ymm, m256 VEX.256 -mavx10.2

_mm256_load_ph __m256h _mm256_load_ph(const void *__p)

VMOVAPS ymm, m256 VEX.256 -mavx512fp16

_mm256_load_ps __m256 _mm256_load_ps(const float *__p)

VMOVAPS ymm, m256 VEX.256 -mavx

_mm256_store_pbh void _mm256_store_pbh(void *__P, __m256bh __A)

VMOVAPS m256, ymm VEX.256 -mavx10.2

_mm256_store_ph void _mm256_store_ph(void *__P, __m256h __A)

VMOVAPS m256, ymm VEX.256 -mavx512fp16

_mm256_store_ps void _mm256_store_ps(float *__p, __m256 __a)

VMOVAPS m256, ymm VEX.256 -mavx

_mm256_mask_blend_ps __m256 _mm256_mask_blend_ps(__mmask8 __U, __m256 __A, __m256 __W)

VMOVAPS ymm {k}, ymm EVEX.256 -mavx512vl

_mm256_mask_load_ps __m256 _mm256_mask_load_ps(__m256 __W, __mmask8 __U, const void *__P)

VMOVAPS ymm {k}, m256 EVEX.256 -mavx512vl

_mm256_mask_mov_ps __m256 _mm256_mask_mov_ps(__m256 __W, __mmask8 __U, __m256 __A)

VMOVAPS ymm {k}, ymm EVEX.256 -mavx512vl

_mm256_mask_store_ps void _mm256_mask_store_ps(void *__P, __mmask8 __U, __m256 __A)

VMOVAPS m256 {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_load_ps __m256 _mm256_maskz_load_ps(__mmask8 __U, const void *__P)

VMOVAPS ymm {k}{z}, m256 EVEX.256 -mavx512vl

_mm256_maskz_mov_ps __m256 _mm256_maskz_mov_ps(__mmask8 __U, __m256 __A)

VMOVAPS ymm {k}{z}, ymm EVEX.256 -mavx512vl

_mm512_load_pbh __m512bh _mm512_load_pbh(const void *__p)

VMOVAPS zmm, m512 EVEX.512 -mavx10.2

_mm512_load_ph __m512h _mm512_load_ph(const void *__p)

VMOVAPS zmm, m512 EVEX.512 -mavx512fp16

_mm512_load_ps __m512 _mm512_load_ps(const void *__p)

VMOVAPS zmm, m512 EVEX.512 -mavx512f

_mm512_store_pbh void _mm512_store_pbh(void *__P, __m512bh __A)

VMOVAPS m512, zmm EVEX.512 -mavx10.2

_mm512_store_ph void _mm512_store_ph(void *__P, __m512h __A)

VMOVAPS m512, zmm EVEX.512 -mavx512fp16

_mm512_store_ps void _mm512_store_ps(void *__P, __m512 __A)

VMOVAPS m512, zmm EVEX.512 -mavx512f

_mm512_mask_blend_ps __m512 _mm512_mask_blend_ps(__mmask16 __U, __m512 __A, __m512 __W)

VMOVAPS zmm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_load_ps __m512 _mm512_mask_load_ps(__m512 __W, __mmask16 __U, const void *__P)

VMOVAPS zmm {k}, m512 EVEX.512 -mavx512f

_mm512_mask_mov_ps __m512 _mm512_mask_mov_ps(__m512 __W, __mmask16 __U, __m512 __A)

VMOVAPS zmm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_store_ps void _mm512_mask_store_ps(void *__P, __mmask16 __U, __m512 __A)

VMOVAPS m512 {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_load_ps __m512 _mm512_maskz_load_ps(__mmask16 __U, const void *__P)

VMOVAPS zmm {k}{z}, m512 EVEX.512 -mavx512f

_mm512_maskz_mov_ps __m512 _mm512_maskz_mov_ps(__mmask16 __U, __m512 __A)

VMOVAPS zmm {k}{z}, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.