VMOVAPS

VMOVAPS is MOVAPS in VEX and EVEX encodings: a copy of packed singles, bits not interpreted, between vector registers or between a register and aligned memory. The MOVAPS page covers its use for any kind of data and its two register encodings. What changes:

• Alignment grows with the width. A memory operand must be aligned to 16 bytes for xmm, 32 for ymm and 64 for zmm, or the instruction raises #GP. A write mask does not relax this: Intel’s table of exception class E1 lists the alignment fault without the condition that exempts masked-out elements from other memory faults.
• Clearing above the width. MOVAPS leaves bits 128 and up of its destination register alone; VEX and EVEX forms clear them above their own width. On Zen 5, vmovaps xmm12, xmm6 left bits 128 to 511 of ZMM12 zero.
• Masks and more registers. EVEX (AVX512F, or AVX10.1) adds a write mask per single, merging or zeroing on loads, and the registers 16 to 31. VMOVAPD, VMOVDQA32 and VMOVDQA64 mask doubles, doublewords and quadwords instead.

In compiled code#

At -O2 with -march=x86-64-v3 or -v4, GCC 14 and Clang 23 copy vector registers of floats with VMOVAPS, and Clang copies integer vectors with it too, where GCC uses VMOVDQA or VMOVDQA64. Both emit it for _mm256_load_ps and _mm256_store_ps, and Clang also for _mm256_load_si256 and the 512-bit _mm512_load_si512. A masked _mm512_maskz_load_ps becomes vmovaps zmm0{k1}{z}, [rdi] in both.

For data whose alignment they cannot see, compilers use VMOVUPS instead, and AMD’s Zen 5 guide says the two perform the same on aligned data (Section 2.6.2): what VMOVAPS adds is the check, which turns a misaligned pointer into a fault rather than a slower access.

Zen 5’s 17 recorded cases cover every form, the masked loads and stores included, all at an aligned address.

In the optimization guide

What the optimization guide says about VMOVAPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Move elimination: A register-to-register copy can be made at renaming, by pointing the destination at the physical register of the source; the move then has no latency and uses no execution unit.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        mem.d[i] = zmm2.d[i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-1

EVEX forms

AVX512-E1

Attributes

What else XED records about the forms. How to read.

Memory forms

aligned memory operand

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVAPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VHADDPD
• VHADDPS
• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP

All 253 AVX instructions

More AVX10.1 instructions

• VINSERTF64X2
• VINSERTF64X4
• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD

All 686 AVX10.1 instructions