x86-64.net

Instruction

VMOVD

Moves 32 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.

Extensions
Forms
11 (4 VEX, 7 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVD xmm, m32 VMOVD_XMMdq_MEMdVEX.128.66.0F.W0 6E /rAVX
VMOVD m32, xmm VMOVD_MEMd_XMMdVEX.128.66.0F.W0 7E /rAVX
VMOVD xmm, r32 VMOVD_XMMdq_GPR32dVEX.128.66.0F.W0 6E /rAVX
VMOVD r32, xmm VMOVD_GPR32d_XMMdVEX.128.66.0F.W0 7E /rAVX
VMOVD xmm, r32 VMOVD_XMMu32_GPR32u32_AVX512EVEX.128.66.0F.W0 6E /rAVX10.1 or AVX512F
VMOVD xmm, m32 VMOVD_XMMu32_MEMu32_AVX512EVEX.128.66.0F.W0 6E /rAVX10.1 or AVX512F
VMOVD r32, xmm VMOVD_GPR32u32_XMMu32_AVX512EVEX.128.66.0F.W0 7E /rAVX10.1 or AVX512F
VMOVD m32, xmm VMOVD_MEMu32_XMMu32_AVX512EVEX.128.66.0F.W0 7E /rAVX10.1 or AVX512F
VMOVD xmm, xmm VMOVD_XMMu32_XMMu32_AVX512_MOVZXCEVEX.128.F3.0F.W0 7E /r
EVEX.128.66.0F.W0 D6 /r		AVX10.2
VMOVD xmm, m32 VMOVD_XMMu32_MEMu32_AVX512_MOVZXCEVEX.128.F3.0F.W0 7E /rAVX10.2
VMOVD m32, xmm VMOVD_MEMu32_XMMu32_AVX512_MOVZXCEVEX.128.66.0F.W0 D6 /rAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtsi128_si32 int _mm_cvtsi128_si32(__m128i __a)

VMOVD r32, xmm VEX.128 -mavxwith AVX enabled

_mm_cvtsi32_si128 __m128i _mm_cvtsi32_si128(int __a)

VMOVD xmm, r32 VEX.128 -mavxwith AVX enabled

_mm_loadu_si32 __m128i _mm_loadu_si32(const void *__a)

VMOVD xmm, m32 VEX.128 -mavxwith AVX enabled

_mm_move_epi32 __m128i _mm_move_epi32(__m128i __A)

VMOVD xmm, xmm EVEX.128 -mavx10.2

_mm_storeu_si32 void _mm_storeu_si32(void *__p, __m128i __b)

VMOVD m32, xmm VEX.128 -mavxwith AVX enabled

_mm512_cvtsi512_si32 int _mm512_cvtsi512_si32(__m512i __A)

VMOVD r32, xmm VEX.128 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512_MOVZXC_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.