VMOVD instruction (AVX, AVX10.1, AVX10.2)

VMOVD is the VEX and EVEX form of MOVD, whose page covers the 32-bit copies compilers make with it. Into an XMM register the newer encodings zero every bit above 31, where the legacy form keeps bits 128 and up. Only a 128-bit form exists: VEX.L = 1 or a VEX.vvvv other than 1111b raises #UD in both vendors’ manuals, and so does an EVEX.vvvv other than 1111b (AMD’s in its table of illegal EVEX encodings, Section 3.2.4). The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1, which reaches XMM16 to XMM31 but takes no mask. With W1 the same opcodes are VMOVQ.

On Zen 5, the recorded vmovd xmm12, dword ptr [mem] cleared bits 511:32 of ZMM12, and {evex} vmovd dword ptr [mem], xmm5 wrote four bytes and left the next ones alone.

A copy between vector registers

AVX10.2 adds the form the older encodings lack, VMOVD from XMM to XMM, which keeps the low doubleword and zeroes the rest. It reuses VMOVQ’s register-copy opcodes, F3 0F 7E and 66 0F D6, with EVEX.W0 where VMOVQ has W1. Zen 5 has no AVX10.2, so these forms were not run.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or x86-64-v4, GCC 14 and Clang 23 emit VMOVD where MOVD’s page shows MOVD. The zeroing makes a zero-extended vector free: for _mm256_zextsi128_si256(_mm_cvtsi32_si128(x)) Clang emits only vmovd xmm0, edi, while GCC adds a vmovdqa xmm0, xmm0 that changes nothing. Keeping only element 0 of four ints, v & (v4si){-1, 0, 0, 0}, takes Clang a VXORPS and a VBLENDPS at -v4, and with -mavx10.2 added the single vmovd xmm0, xmm0.

AMD’s latency spreadsheet for Zen 5 lists VMOVD from a general-purpose register as one macro-op in its VEX and EVEX rows, where legacy MOVD takes two. Only the EVEX rows give latencies: 1 cycle for a move out of the XMM register, on FP4 or FP5, and 0 for a move into it.

Forms

Every encoding of VMOVD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVD xmm, m32` VMOVD_XMMdq_MEMd	`VEX.128.66.0F.W0 6E /r`	AVX
`VMOVD m32, xmm` VMOVD_MEMd_XMMd	`VEX.128.66.0F.W0 7E /r`	AVX
`VMOVD xmm, r32` VMOVD_XMMdq_GPR32d	`VEX.128.66.0F.W0 6E /r`	AVX
`VMOVD r32, xmm` VMOVD_GPR32d_XMMd	`VEX.128.66.0F.W0 7E /r`	AVX
`VMOVD xmm, r32` VMOVD_XMMu32_GPR32u32_AVX512	`EVEX.128.66.0F.W0 6E /r`	AVX10.1 or AVX512F
`VMOVD xmm, m32` VMOVD_XMMu32_MEMu32_AVX512	`EVEX.128.66.0F.W0 6E /r`	AVX10.1 or AVX512F
`VMOVD r32, xmm` VMOVD_GPR32u32_XMMu32_AVX512	`EVEX.128.66.0F.W0 7E /r`	AVX10.1 or AVX512F
`VMOVD m32, xmm` VMOVD_MEMu32_XMMu32_AVX512	`EVEX.128.66.0F.W0 7E /r`	AVX10.1 or AVX512F
`VMOVD xmm, xmm` VMOVD_XMMu32_XMMu32_AVX512_MOVZXC	`EVEX.128.F3.0F.W0 7E /r` `EVEX.128.66.0F.W0 D6 /r`	AVX10.2
`VMOVD xmm, m32` VMOVD_XMMu32_MEMu32_AVX512_MOVZXC	`EVEX.128.F3.0F.W0 7E /r`	AVX10.2
`VMOVD m32, xmm` VMOVD_MEMu32_XMMu32_AVX512_MOVZXC	`EVEX.128.66.0F.W0 D6 /r`	AVX10.2

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, m32`	`m32, xmm`	`xmm, r32`	`r32, xmm`	`xmm, m32`
Sandy Bridge	6 / 0.5p23	1 / 1p4 p23	1 / 1p5	2 / 1p0
Haswell, Broadwell	5 / 0.5p23	1 / 1p2347	1 / 1p5	1 / 1p0
Skylake	5 / 0.5p23	1 / 1p2347	1 / 1p5	2 / 1p0
Skylake-SP	5 / 0.5p23	1 / 1p2347	1 / 1p5	2 / 1p0	6 / 0.5p015
Ice Lake	5 / 0.5p23	1 / 0.5p4789	1 / 1p5	2 / 1p0	6 / 0.5p015
Alder Lake	7 / 0.33p2 p3 p10	12 / 0.5p4789	3 / 1p5	3 / 1p0
Sapphire Rapids	7 / 0.33p2 p3 p10	12 / 0.5p4789	3 / 1p5	3 / 1p0	7 / 0.33p2 p3 p10
Lunar Lake	6 / 0.33p20 p21 p22	12 / 0.5p10 p11 p25 p26 p27	3 / 0.33p135	3 / 0.5V0 V1
Piledriver	5 / 1.5FPMAL FPU0 FPU1	2 / 1.5AGLU01 FPSTO FPU2 FPU3 Store	11 / 1FPFMA FPU0 FPU1	11 / 1EX0 FPFMA FPU0
Zen	8 / 0.5AGU0 AGU1	1 / 0.5AGU0 AGU1	3 / 1FPU2	2 / 1FPU2
Zen 2	8 / 0.33AGU0 AGU1 AGU2	1 / 0.33AGU0 AGU1 AGU2	3 / 1FPU2	2 / 1FPU2
Zen 3	8 / 0.5FP45 LSU Load	1 / 1FP45 FPSt LSU Store	1 / 1FP45	1 / 1FP45
Zen 4	8 / 0.5FP45 LSU Load	1 / 1FP45 FPSt LSU Store	1 / 1FP45	1 / 1FP45	8 / 0.5FP45 LSU Load
Jaguar	5 / 1FPU0 FPU1 VALU0 VALU1	2 / 1FPU1	8 / 0.5FPA FPM FPU0 FPU1	4 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The doubleword in r32 goes to the low end of xmm1, and the rest of xmm1 is zeroed.VMOVD xmm, r/m32

Result doublewords 3 to 0: 0, 0, 0, a0.

The low doubleword of xmm2 goes to m32.VMOVD r/m32, xmm

m32 receives doubleword 0 of xmm2: a0.

The low doubleword of xmm2 goes to the low end of xmm1, and the rest of xmm1 is zeroed.VMOVD xmm, xmm

Result doublewords 3 to 0: 0, 0, 0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VMOVD xmm, r/m32

xmm1.write(src2.d[0])  # zeroed from bit 32 up

Run on AMD Zen 5 (EPYC 9645): 4 cases. The AVX10.2 forms were not run: none of these processors has AVX10.2.

VMOVD r/m32, xmm

dest.write(xmm2.d[0])  # a register: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases. The AVX10.2 forms were not run: none of these processors has AVX10.2.

VMOVD xmm, xmm

xmm1.write(xmm2.d[0])  # zeroed from bit 32 up

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVD xmm, r/m32` `VMOVD xmm, xmm/m32`
`xmm`	explicit	write
`r/m32, xmm/m32`	explicit	read
`VMOVD r/m32, xmm`
`r/m32`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtsi128_si32` `int _mm_cvtsi128_si32(__m128i __a)`	`VMOVD r32, xmm` VEX.128 -mavxwith AVX enabled
`_mm_cvtsi32_si128` `__m128i _mm_cvtsi32_si128(int __a)`	`VMOVD xmm, r32` VEX.128 -mavxwith AVX enabled
`_mm_loadu_si32` `__m128i _mm_loadu_si32(const void *__a)`	`VMOVD xmm, m32` VEX.128 -mavxwith AVX enabled
`_mm_move_epi32` `__m128i _mm_move_epi32(__m128i __A)`	`VMOVD xmm, xmm` EVEX.128 -mavx10.2
`_mm_storeu_si32` `void _mm_storeu_si32(void *__p, __m128i __b)`	`VMOVD m32, xmm` VEX.128 -mavxwith AVX enabled
`_mm512_cvtsi512_si32` `int _mm512_cvtsi512_si32(__m512i __A)`	`VMOVD r32, xmm` VEX.128 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
`AVX512_MOVZXC_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

AVX

AVX
CPUID.01H:ECX[28] AVX