VMOVDDUP

VMOVDDUP is the VEX and EVEX form of MOVDDUP, whose page covers the 128-bit broadcast of a double and its place in SSE3. The 128-bit forms still copy the low double, or eight bytes of memory at any alignment, into both halves, and zero the register above. The wider forms do it in each 128-bit lane: a ymm result holds doubles 0, 0, 2, 2 of the source, and its memory operand is 32 bytes, though doubles 1 and 3 are not used. VEX.128 and VEX.256 need AVX; the EVEX forms need AVX512F (with AVX512VL below 512 bits) or AVX10.1, and add a write mask per double but no broadcast. To fill a whole ymm register with one double, VBROADCASTSD is the instruction.

On Zen 5, vmovddup ymm12, ymmword ptr [mem] gave the doubles at offsets 0 and 16 twice each. With masks: vmovddup xmm0{k5}{z}, qword ptr [mem], with bit 1 of K5 clear, kept the memory double in element 0 only and zeroed element 1, and vmovddup zmm0{k4}, zmm31 wrote elements 0, 2, 5, 6 and 7, each from the even double of its lane, and kept elements 1, 3 and 4 of ZMM0.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 compile _mm_set1_pd(*p) and _mm_loaddup_pd(p) to vmovddup xmm0, qword ptr [rdi], and _mm256_set1_pd to VBROADCASTSD. For _mm_movedup_pd(v) Clang emits VMOVDDUP and GCC vpermilpd xmm0, xmm0, 0. For _mm256_movedup_pd(v) and _mm512_movedup_pd(v) on a register, Clang emits vmovddup ymm0, ymm0 and its zmm twin, while GCC stores the register to the stack and runs VMOVDDUP on the copy in memory; from memory, both load and duplicate in one VMOVDDUP.

AMD’s latency spreadsheet for Zen 5 gives the VEX forms one macro-op on pipes FP0 to FP3, a latency of 1 cycle and four per cycle, and the EVEX forms one macro-op on FP1 or FP2, a latency of 2 cycles and two per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    j = i - i % 2
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[j]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDDUP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VHSUBPD
• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD

All 253 AVX instructions

More AVX10.1 instructions

• VINSERTI32X4
• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP

All 686 AVX10.1 instructions