VMOVDQA

VMOVDQA is the VEX form of MOVDQA: a load, store or register copy of 16 or 32 bytes, with memory aligned to that size. The MOVDQA page covers the alignment rule, the #GP that breaks it and the atomicity of aligned 16-byte accesses. What VEX changes:

• 32 bytes, aligned to 32. The VEX.256 forms move a whole YMM register and fault on an address that is a multiple of 16 but not of 32, which a 16-byte habit can miss: a stack slot that the System V rule aligns for SSE is not necessarily aligned for this form.
• An exception among VEX instructions. Most VEX instructions take memory at any address, so VPADDD and its kin fold loads without a check; VMOVDQA keeps one, as do the other aligned moves.
• Clearing above the width. On Zen 5, vmovdqa xmm1, xmm2 left bits 128 to 511 of ZMM1 zero, in both of its encodings (opcodes 6F and 7F, chosen with {load} and {store}).

There is no EVEX VMOVDQA. AVX-512 names the move by the element size of its mask, VMOVDQA32 and VMOVDQA64, and only they reach ZMM registers and XMM16 to XMM31.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v3 uses VMOVDQA for _mm_load_si128, _mm256_load_si256 and their stores, and to copy integer vectors between registers, such as vmovdqa ymm1, ymm0 to save an argument before overwriting it. Clang 23 compiles the same intrinsics to VMOVAPS, the same bits under a float name, but stores the results of an aligned int loop with VMOVDQA. With -march=x86-64-v4, GCC moves 512-bit integer vectors with VMOVDQA64 or VMOVDQA32 and keeps VMOVDQA for ymm registers that VEX can name.

Where the alignment cannot be shown, compilers use VMOVDQU instead, which AMD’s Zen 5 guide says performs the same on aligned data (Section 2.6.2). Zen 5’s 8 recorded cases cover the loads, the stores and both register encodings at 128 and 256 bits, all at an aligned address.

In the optimization guide

What the optimization guide says about VMOVDQA, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Move elimination: A register-to-register copy can be made at renaming, by pointing the destination at the physical register of the source; the move then has no latency and uses no execution unit.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-1

Attributes

What else XED records about the forms. How to read.

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQA, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VHSUBPS
• VINSERTF128
• VINSERTPS
• VLDDQU
• VLDMXCSR
• VMASKMOVDQU
• VMASKMOVPD
• VMASKMOVPS
• VMAXPD
• VMAXPS
• VMAXSD
• VMAXSS
• VMINPD
• VMINPS
• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS

All 253 AVX instructions