VMOVDQA32

VMOVDQA32 is the AVX-512 form of MOVDQA with a write mask that selects doublewords: an aligned load, store or register copy of 16, 32 or 64 bytes. The address must be aligned to the full width of the move even where the mask leaves elements out. Unmasked it moves the same bits as VMOVDQA64, whose page covers registers 16 to 31 and the names the compilers give a plain 512-bit copy. The doubleword mask is what this name adds:

• Merging. On Zen 5, vmovdqa32 zmm9{k5}, [mem] with D5E1h in the low 16 bits of K5 loaded doublewords 0, 5 to 8, 10, 12, 14 and 15 and kept the other seven of ZMM9.
• Zeroing. vmovdqa32 ymm5{k3}{z}, ymm5 with EBh in the low byte of K3 zeroed doublewords 2 and 4 and the bits from 256 up.
• Stores write only the selected doublewords and leave the rest of the memory alone. They cannot zero: the SDM makes a store with {z} raise #UD (Table 2-42).

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 aligns global int arrays to 64 bytes and loads and stores them with VMOVDQA32 in vectorized loops; Clang 23 keeps to ymm registers and VMOVDQU there. Both compile _mm512_mask_load_epi32, _mm512_maskz_load_epi32, _mm512_mask_store_epi32 and _mm512_mask_blend_epi32 to VMOVDQA32.

Conditions become masks. For b[i] > 0 ? c[i] : 0, GCC loads c with a zero-masked VMOVDQA32 under the mask of a VPCMPD. For if (a[i] > b[i]) a[i] += b[i]; it adds all elements and stores the sums with a merge-masked VMOVDQA32, skipping the store when KORTESTW finds no element selected. Intel’s optimization manual compares such variants: in its Example 17-6, computing both outcomes of a condition and merging them with a masked VMOVDQA32 before the store ran 1.23 times as fast as masking each arithmetic step, which chains them (Section 17.2.3).

AMD’s Zen 5 latency spreadsheet gives the masked EVEX forms one cycle and four per cycle on any of the four vector pipes. Zen 5’s 9 recorded cases cover every form, masked, at all three widths.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = src2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 32):
    if k1[i]:
        mem.d[i] = zmm2.d[i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E1

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

aligned memory operand; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQA32, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VINSERTI32X8
• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP

All 686 AVX10.1 instructions