VMOVDQA64

VMOVDQA64 is the AVX-512 form of MOVDQA: an aligned load, store or register copy of 16, 32 or 64 bytes, with a write mask that selects quadwords. The MOVDQA page covers the alignment rule and the atomicity of aligned moves; here the rule follows the width, 16, 32 or 64 bytes, and it holds even for elements the mask leaves out.

Without a mask the element size does not matter, and VMOVDQA64 is the same move as VMOVDQA32 or the VEX VMOVDQA. What it adds:

• Quadword masks. A masked load or register copy keeps the unselected quadwords of the destination, or zeroes them with {z}; a masked store leaves the memory of the unselected ones untouched. On Zen 5, vmovdqa64 zmm1{k4}, zmm2 with 0E5h in the low byte of K4 took quadwords 0, 2, 5, 6 and 7 from ZMM2 and kept 1, 3 and 4, and vmovdqa64 ymm24{k7}{z}, ymm3 with low mask bits 0011b copied two quadwords and zeroed the rest of ZMM24.
• Registers 16 to 31 and ZMM registers, which VEX cannot name.

In compiled code#

GCC 14 at -O2 with -march=x86-64-v4 uses VMOVDQA64 for unmasked copies of 512-bit integer vectors, between registers and for _mm512_load_si512 and _mm512_store_si512. Clang 23 uses VMOVAPS for those and VMOVDQA64 only where a mask makes the element size matter: _mm512_mask_load_epi64, _mm512_maskz_load_epi64 and _mm512_mask_store_epi64 compile to it in both compilers.

A merging register copy is a blend: both compile _mm512_mask_blend_epi64(m, a, b) to vmovdqa64 zmm0{k1}, zmm1, which writes b’s quadwords over a in place. With {z} it is a select against zero, and that is how GCC 14 turns a comparison’s mask into a vector: after a VPCMPEQD into K1, a zero-masked VMOVDQA32 of an all-ones register gives -1 where elements matched and 0 elsewhere.

For unaligned data the masked move is VMOVDQU64, whose masked-out elements also raise no fault, so it can stop at the end of a buffer; VMOVDQU8 shows that use. Zen 5’s 9 recorded cases cover every form, all at an aligned address.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = src2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:
        mem.q[i] = zmm2.q[i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E1

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

aligned memory operand; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQA64, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VINSERTI64X2
• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS

All 686 AVX10.1 instructions