Instruction
VMOVDQA64
Moves integer vectors between registers and aligned memory, masked at quadword granularity.
- Extensions
- Forms
- 9 (9 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMOVDQA64 zmm {k}{z}, zmm
VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 | EVEX.512.66.0F.W1 6F /rEVEX.512.66.0F.W1 7F /r | AVX10.1 or AVX512F |
VMOVDQA64 zmm {k}{z}, m512
VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 | EVEX.512.66.0F.W1 6F /r | AVX10.1 or AVX512F |
VMOVDQA64 m512 {k}, zmm
VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 | EVEX.512.66.0F.W1 7F /r | AVX10.1 or AVX512F |
VMOVDQA64 xmm {k}{z}, xmm
VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 | EVEX.128.66.0F.W1 6F /rEVEX.128.66.0F.W1 7F /r | AVX10.1 or AVX512F + AVX512VL |
VMOVDQA64 xmm {k}{z}, m128
VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 | EVEX.128.66.0F.W1 6F /r | AVX10.1 or AVX512F + AVX512VL |
VMOVDQA64 m128 {k}, xmm
VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 | EVEX.128.66.0F.W1 7F /r | AVX10.1 or AVX512F + AVX512VL |
VMOVDQA64 ymm {k}{z}, ymm
VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 | EVEX.256.66.0F.W1 6F /rEVEX.256.66.0F.W1 7F /r | AVX10.1 or AVX512F + AVX512VL |
VMOVDQA64 ymm {k}{z}, m256
VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 | EVEX.256.66.0F.W1 6F /r | AVX10.1 or AVX512F + AVX512VL |
VMOVDQA64 m256 {k}, ymm
VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 | EVEX.256.66.0F.W1 7F /r | AVX10.1 or AVX512F + AVX512VL |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMOVDQA64, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_mask_alignr_epi64
__m128i _mm_mask_alignr_epi64(__m128i W, __mmask8 U, __m128i A, __m128i B, const int imm) |
|
_mm_mask_blend_epi64
__m128i _mm_mask_blend_epi64(__mmask8 __U, __m128i __A, __m128i __W) |
|
_mm_mask_load_epi64
__m128i _mm_mask_load_epi64(__m128i __W, __mmask8 __U, const void *__P) |
|
_mm_mask_mov_epi64
__m128i _mm_mask_mov_epi64(__m128i __W, __mmask8 __U, __m128i __A) |
|
_mm_mask_store_epi64
void _mm_mask_store_epi64(void *__P, __mmask8 __U, __m128i __A) |
|
_mm_maskz_alignr_epi64
__m128i _mm_maskz_alignr_epi64(__mmask8 U, __m128i A, __m128i B, const int imm) |
|
_mm_maskz_load_epi64
__m128i _mm_maskz_load_epi64(__mmask8 __U, const void *__P) |
|
_mm_maskz_mov_epi64
__m128i _mm_maskz_mov_epi64(__mmask8 __U, __m128i __A) |
|
_mm256_mask_blend_epi64
__m256i _mm256_mask_blend_epi64(__mmask8 __U, __m256i __A, __m256i __W) |
|
_mm256_mask_load_epi64
__m256i _mm256_mask_load_epi64(__m256i __W, __mmask8 __U, const void *__P) |
|
_mm256_mask_mov_epi64
__m256i _mm256_mask_mov_epi64(__m256i __W, __mmask8 __U, __m256i __A) |
|
_mm256_mask_store_epi64
void _mm256_mask_store_epi64(void *__P, __mmask8 __U, __m256i __A) |
|
_mm256_maskz_load_epi64
__m256i _mm256_maskz_load_epi64(__mmask8 __U, const void *__P) |
|
_mm256_maskz_mov_epi64
__m256i _mm256_maskz_mov_epi64(__mmask8 __U, __m256i __A) |
|
_mm512_load_epi64
__m512i _mm512_load_epi64(const void *__P) |
|
_mm512_load_si512
__m512i _mm512_load_si512(const void *__P) |
|
_mm512_store_epi64
void _mm512_store_epi64(void *__P, __m512i __A) |
|
_mm512_store_si512
void _mm512_store_si512(void *__P, __m512i __A) |
|
_mm512_mask_blend_epi64
__m512i _mm512_mask_blend_epi64(__mmask8 __U, __m512i __A, __m512i __W) |
|
_mm512_mask_load_epi64
__m512i _mm512_mask_load_epi64(__m512i __W, __mmask8 __U, const void *__P) |
|
_mm512_mask_mov_epi64
__m512i _mm512_mask_mov_epi64(__m512i __W, __mmask8 __U, __m512i __A) |
|
_mm512_mask_store_epi64
void _mm512_mask_store_epi64(void *__P, __mmask8 __U, __m512i __A) |
|
_mm512_maskz_load_epi64
__m512i _mm512_maskz_load_epi64(__mmask8 __U, const void *__P) |
|
_mm512_maskz_mov_epi64
__m512i _mm512_maskz_mov_epi64(__mmask8 __U, __m512i __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512F_512 | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
AVX512F_128 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512F_256 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.