VMOVDQU instruction (AVX)

VMOVDQU is the VEX form of MOVDQU: a load, store or register copy of 16 or 32 bytes at any address. The MOVDQU page covers the move itself, the cost of crossing a cache line and what the manuals say about atomicity. What VEX changes:

256 bits. The VEX.256 forms move a whole YMM register, the usual unaligned load and store of AVX2 integer code.
Clearing above the width. The 128-bit forms clear bits 128 and up of a destination register, which MOVDQU leaves alone. On Zen 5, vmovdqu xmm4, xmm4 kept the low 16 bytes of ZMM4 and zeroed the other 48.
No alignment rule elsewhere. VEX instructions such as VPADDD take memory operands at any address, so a load can often be folded into the arithmetic and no VMOVDQU is needed at all.

There is no EVEX VMOVDQU: AVX-512 splits it by element size for masking, into VMOVDQU8, VMOVDQU16, VMOVDQU32 and VMOVDQU64, which also reach ZMM registers and XMM16 to XMM31.

Which move the compilers pick

The encodings move the same bits, so the choice is a matter of taste:

-O2 with	GCC 14	Clang 23
`-march=x86-64-v3`, `_mm256_loadu_si256`	VMOVDQU	VMOVUPS
`-march=x86-64-v3`, `int` loop	VMOVDQU	VMOVDQU
`-march=x86-64-v3`, 32-byte `memcpy`	VMOVDQU	VMOVUPS
`-march=x86-64-v4`, `int` loop	VMOVDQU32 on zmm	VMOVDQU on ymm
`-march=x86-64-v4`, 64-byte `memcpy`	VMOVDQU8 on zmm	two VMOVUPS on ymm

The loop is a[i] = b[i] + c[i] over 1,024 ints, where both compilers fold one load into VPADDD and move the other operand and the result with these instructions. AMD’s Zen 5 guide states that the aligned and unaligned forms perform the same on aligned data, and that aligning 256-bit vectors to 32 bytes still pays (Section 2.6.2).

Zen 5’s 8 recorded cases cover the loads, the stores and both register encodings (opcodes 6F and 7F) at 128 and 256 bits.

Forms

Every encoding of VMOVDQU that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVDQU xmm, m128` VMOVDQU_XMMdq_MEMdq	`VEX.128.F3.0F.WIG 6F /r`	AVX
`VMOVDQU xmm, xmm` VMOVDQU_XMMdq_XMMdq_6F	`VEX.128.F3.0F.WIG 6F /r`	AVX
`VMOVDQU ymm, m256` VMOVDQU_YMMqq_MEMqq	`VEX.256.F3.0F.WIG 6F /r`	AVX
`VMOVDQU ymm, ymm` VMOVDQU_YMMqq_YMMqq_6F	`VEX.256.F3.0F.WIG 6F /r`	AVX
`VMOVDQU m128, xmm` VMOVDQU_MEMdq_XMMdq	`VEX.128.F3.0F.WIG 7F /r`	AVX
`VMOVDQU xmm, xmm` VMOVDQU_XMMdq_XMMdq_7F	`VEX.128.F3.0F.WIG 7F /r`	AVX
`VMOVDQU m256, ymm` VMOVDQU_MEMqq_YMMqq	`VEX.256.F3.0F.WIG 7F /r`	AVX
`VMOVDQU ymm, ymm` VMOVDQU_YMMqq_YMMqq_7F	`VEX.256.F3.0F.WIG 7F /r`	AVX

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each doubleword is copied to the same place.

Every doubleword works alike: 4 and 8 doublewords in the xmm and ymm forms. The store forms copy the same way, from the register to memory.

Result doubleword i is doubleword i of xmm2. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(src2.read())
# a register destination is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVDQU xmm, xmm/m128` `VMOVDQU ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm/m128, ymm/m256`	explicit	read
`VMOVDQU xmm/m128, xmm` `VMOVDQU ymm/m256, ymm`
`xmm/m128, ymm/m256`	explicit	write
`xmm, ymm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4M

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQU, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadu_epi16` `__m128i _mm_loadu_epi16(const void *__P)`	`VMOVDQU xmm, m128` VEX.128 -mavx512vl -mavx512bw
`_mm_loadu_epi32` `__m128i _mm_loadu_epi32(const void *__P)`	`VMOVDQU xmm, m128` VEX.128 -mavx512vl
`_mm_loadu_epi64` `__m128i _mm_loadu_epi64(const void *__P)`	`VMOVDQU xmm, m128` VEX.128 -mavx512vl
`_mm_loadu_epi8` `__m128i _mm_loadu_epi8(const void *__P)`	`VMOVDQU xmm, m128` VEX.128 -mavx512vl -mavx512bw
`_mm_loadu_si128` `__m128i _mm_loadu_si128(const __m128i_u *__p)`	`VMOVDQU xmm, m128` VEX.128 -mavxwith AVX enabled
`_mm_storeu_epi16` `void _mm_storeu_epi16(void *__P, __m128i __A)`	`VMOVDQU m128, xmm` VEX.128 -mavx512vl -mavx512bw
`_mm_storeu_epi32` `void _mm_storeu_epi32(void *__P, __m128i __A)`	`VMOVDQU m128, xmm` VEX.128 -mavx512vl
`_mm_storeu_epi64` `void _mm_storeu_epi64(void *__P, __m128i __A)`	`VMOVDQU m128, xmm` VEX.128 -mavx512vl
`_mm_storeu_epi8` `void _mm_storeu_epi8(void *__P, __m128i __A)`	`VMOVDQU m128, xmm` VEX.128 -mavx512vl -mavx512bw
`_mm256_loadu_epi16` `__m256i _mm256_loadu_epi16(const void *__P)`	`VMOVDQU ymm, m256` VEX.256 -mavx512vl -mavx512bw
`_mm256_loadu_epi32` `__m256i _mm256_loadu_epi32(const void *__P)`	`VMOVDQU ymm, m256` VEX.256 -mavx512vl
`_mm256_loadu_epi64` `__m256i _mm256_loadu_epi64(const void *__P)`	`VMOVDQU ymm, m256` VEX.256 -mavx512vl
`_mm256_loadu_epi8` `__m256i _mm256_loadu_epi8(const void *__P)`	`VMOVDQU ymm, m256` VEX.256 -mavx512vl -mavx512bw
`_mm256_loadu_si256` `__m256i _mm256_loadu_si256(const __m256i_u *__p)`	`VMOVDQU ymm, m256` VEX.256 -mavxClang emits the equivalent VMOVUPS
`_mm256_storeu_epi16` `void _mm256_storeu_epi16(void *__P, __m256i __A)`	`VMOVDQU m256, ymm` VEX.256 -mavx512vl -mavx512bw
`_mm256_storeu_epi32` `void _mm256_storeu_epi32(void *__P, __m256i __A)`	`VMOVDQU m256, ymm` VEX.256 -mavx512vl
`_mm256_storeu_epi64` `void _mm256_storeu_epi64(void *__P, __m256i __A)`	`VMOVDQU m256, ymm` VEX.256 -mavx512vl
`_mm256_storeu_epi8` `void _mm256_storeu_epi8(void *__P, __m256i __A)`	`VMOVDQU m256, ymm` VEX.256 -mavx512vl -mavx512bw
`_mm256_storeu_si256` `void _mm256_storeu_si256(__m256i_u *__p, __m256i __a)`	`VMOVDQU m256, ymm` VEX.256 -mavxClang emits the equivalent VMOVUPS

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

Which move the compilers pick#