VMOVDQU16

VMOVDQU16 is the masked move of AVX512BW at word granularity: one bit of the mask register per word, 8, 16 or 32 of them, decides whether that word is loaded, stored or copied. Without a mask it is the same unaligned move as VMOVDQU8, whose page explains masked loads at the end of a buffer, fault suppression, zeroing and masked stores; only the element the mask counts in differs. A mask for a ZMM register is 32 bits, filled with KMOVD.

Recorded on Zen 5#

The 63 recorded cases cover loads, stores and both register-to-register encodings at all three widths, the memory forms at an address 16 bytes past a 64-byte boundary; none faulted.

• Masked store. vmovdqu16 zmmword ptr [mem]{k3}, zmm5, with 55555555h in the low 32 bits of K3, wrote the 16 even words and left the odd words of memory as they were.
• Zeroing. vmovdqu16 zmm7{k6}{z}, zmmword ptr [mem], with 55555555h in K6 as well, loaded the even words and cleared the odd ones.
• The store-form encoding between registers, {store}, takes {z} as well: vmovdqu16 xmm7{k6}{z}, xmm12 kept words 0, 2, 4 and 6 of XMM12 by 55h and zeroed the rest.

In compiled code#

GCC 14 and Clang 23 at -O2 compile _mm512_maskz_loadu_epi16, _mm512_mask_storeu_epi16 and _mm512_mask_blend_epi16 to it, and a tail load with a mask from _bzhi_u32(~0u, n) to BZHI, KMOVD and a zero-masked VMOVDQU16. With -march=sapphirerapids it also moves half-precision data: the SDM defines no packed half-precision move or blend, so both compilers use VMOVDQU16 for _mm512_mask_blend_ph and for a select between _Float16 arrays, after a VCMPPH has written the mask.

AMD’s Zen 5 latency spreadsheet lists VMOVDQU16 with VMOVDQU8: one macro-op of one cycle on any of the four vector pipes, four per cycle, and notes that with K0 the register, load and store forms are handled as plain moves, loads and stores.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = src2.w[i]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 16):
    if k1[i]:
        mem.w[i] = zmm2.w[i]
    # else: mem.w[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQU16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VINSERTI64X4
• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD

All 686 AVX10.1 instructions