Instruction
VMOVDQU16
Moves integer vectors between registers and memory without an alignment requirement, masked at word granularity.
- Extensions
- Forms
- 9 (9 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMOVDQU16 xmm {k}{z}, xmm
VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 | EVEX.128.F2.0F.W1 6F /rEVEX.128.F2.0F.W1 7F /r | AVX10.1 or AVX512BW + AVX512VL |
VMOVDQU16 xmm {k}{z}, m128
VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 | EVEX.128.F2.0F.W1 6F /r | AVX10.1 or AVX512BW + AVX512VL |
VMOVDQU16 m128 {k}, xmm
VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 | EVEX.128.F2.0F.W1 7F /r | AVX10.1 or AVX512BW + AVX512VL |
VMOVDQU16 ymm {k}{z}, ymm
VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 | EVEX.256.F2.0F.W1 6F /rEVEX.256.F2.0F.W1 7F /r | AVX10.1 or AVX512BW + AVX512VL |
VMOVDQU16 ymm {k}{z}, m256
VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 | EVEX.256.F2.0F.W1 6F /r | AVX10.1 or AVX512BW + AVX512VL |
VMOVDQU16 m256 {k}, ymm
VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 | EVEX.256.F2.0F.W1 7F /r | AVX10.1 or AVX512BW + AVX512VL |
VMOVDQU16 zmm {k}{z}, zmm
VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 | EVEX.512.F2.0F.W1 6F /rEVEX.512.F2.0F.W1 7F /r | AVX10.1 or AVX512BW |
VMOVDQU16 zmm {k}{z}, m512
VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 | EVEX.512.F2.0F.W1 6F /r | AVX10.1 or AVX512BW |
VMOVDQU16 m512 {k}, zmm
VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 | EVEX.512.F2.0F.W1 7F /r | AVX10.1 or AVX512BW |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMOVDQU16, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_mask_blend_epi16
__m128i _mm_mask_blend_epi16(__mmask8 __U, __m128i __A, __m128i __W) |
|
_mm_mask_blend_pbh
__m128bh _mm_mask_blend_pbh(__mmask8 __U, __m128bh __A, __m128bh __W) |
|
_mm_mask_blend_ph
__m128h _mm_mask_blend_ph(__mmask8 __U, __m128h __A, __m128h __W) |
|
_mm_mask_loadu_epi16
__m128i _mm_mask_loadu_epi16(__m128i __W, __mmask8 __U, const void *__P) |
|
_mm_mask_mov_epi16
__m128i _mm_mask_mov_epi16(__m128i __W, __mmask8 __U, __m128i __A) |
|
_mm_mask_store_sbh
void _mm_mask_store_sbh(void *__W, __mmask8 __U, __m128bh __A) |
|
_mm_mask_storeu_epi16
void _mm_mask_storeu_epi16(void *__P, __mmask8 __U, __m128i __A) |
|
_mm_maskz_load_sbh
__m128bh _mm_maskz_load_sbh(__mmask8 __U, const void *__A) |
|
_mm_maskz_loadu_epi16
__m128i _mm_maskz_loadu_epi16(__mmask8 __U, const void *__P) |
|
_mm_maskz_mov_epi16
__m128i _mm_maskz_mov_epi16(__mmask8 __U, __m128i __A) |
|
_mm256_mask_blend_epi16
__m256i _mm256_mask_blend_epi16(__mmask16 __U, __m256i __A, __m256i __W) |
|
_mm256_mask_blend_pbh
__m256bh _mm256_mask_blend_pbh(__mmask16 __U, __m256bh __A, __m256bh __W) |
|
_mm256_mask_blend_ph
__m256h _mm256_mask_blend_ph(__mmask16 __U, __m256h __A, __m256h __W) |
|
_mm256_mask_loadu_epi16
__m256i _mm256_mask_loadu_epi16(__m256i __W, __mmask16 __U, const void *__P) |
|
_mm256_mask_mov_epi16
__m256i _mm256_mask_mov_epi16(__m256i __W, __mmask16 __U, __m256i __A) |
|
_mm256_mask_storeu_epi16
void _mm256_mask_storeu_epi16(void *__P, __mmask16 __U, __m256i __A) |
|
_mm256_maskz_loadu_epi16
__m256i _mm256_maskz_loadu_epi16(__mmask16 __U, const void *__P) |
|
_mm256_maskz_mov_epi16
__m256i _mm256_maskz_mov_epi16(__mmask16 __U, __m256i __A) |
|
_mm512_loadu_epi16
__m512i _mm512_loadu_epi16(const void *__P) |
|
_mm512_storeu_epi16
void _mm512_storeu_epi16(void *__P, __m512i __A) |
|
_mm512_mask_blend_epi16
__m512i _mm512_mask_blend_epi16(__mmask32 __U, __m512i __A, __m512i __W) |
|
_mm512_mask_blend_pbh
__m512bh _mm512_mask_blend_pbh(__mmask32 __U, __m512bh __A, __m512bh __W) |
|
_mm512_mask_blend_ph
__m512h _mm512_mask_blend_ph(__mmask32 __U, __m512h __A, __m512h __W) |
|
_mm512_mask_loadu_epi16
__m512i _mm512_mask_loadu_epi16(__m512i __W, __mmask32 __U, const void *__P) |
|
_mm512_mask_mov_epi16
__m512i _mm512_mask_mov_epi16(__m512i __W, __mmask32 __U, __m512i __A) |
|
_mm512_mask_storeu_epi16
void _mm512_mask_storeu_epi16(void *__P, __mmask32 __U, __m512i __A) |
|
_mm512_maskz_loadu_epi16
__m512i _mm512_maskz_loadu_epi16(__mmask32 __U, const void *__P) |
|
_mm512_maskz_mov_epi16
__m512i _mm512_maskz_mov_epi16(__mmask32 __U, __m512i __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512BW_128 | AVX10.1 or AVX512BW + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512BW_256 | AVX10.1 or AVX512BW + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512BW_512 | AVX10.1 or AVX512BW | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.