VMOVDQU32

VMOVDQU32 is one of the four EVEX encodings of the unaligned integer move: a load, store or register copy of 16, 32 or 64 bytes at any address, as VMOVDQU is in VEX, with a write mask that selects doublewords. Unmasked, it moves the same bits as VMOVDQU8, VMOVDQU16 and VMOVDQU64. The VMOVDQU8 page covers masked loads and stores, whose left-out elements raise no fault, and their use at the end of a buffer. What the doubleword form brings:

• AVX512F alone. VMOVDQU32 and VMOVDQU64 need only AVX512F (or AVX10.1); the byte and word forms need AVX512BW. A loop over int elements can mask its tail on any AVX-512 processor.
• A 16-bit mask for 512 bits. One mask bit per int, so a tail of n elements takes the n low bits of a 16-bit mask. On Zen 5, vmovdqu32 xmm7{k2}{z}, [mem] with 1001b in the low bits of K2 loaded doublewords 0 and 3 and zeroed 1 and 2 and the rest of ZMM7.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compile a tail written with intrinsics, _mm512_maskz_loadu_epi32 and _mm512_mask_storeu_epi32 under a mask made by BZHI of FFFFh and KMOVD, to vmovdqu32 zmm0{k1}{z}, [rsi] and vmovdqu32 [rdi]{k1}, zmm0. Neither masks the tail of a plain C loop at -O2: GCC leaves a loop of unknown count scalar, and Clang finishes one with scalar code.

Unmasked, the element size is only a name, and the compilers differ. GCC loads and stores the zmm registers of a vectorized int loop with VMOVDQU32, a[i] = b[i] + c[i] for example, but compiles _mm512_loadu_si512 to VMOVDQU64. Clang stays with ymm registers and VEX VMOVDQU in the loop, and uses VMOVUPS for the 512-bit intrinsic.

For _mm512_mask_blend_epi32, a merging register copy, both emit the aligned name VMOVDQA32. Zen 5’s 9 recorded cases cover every form, masked, at all three widths, all at an aligned address.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = src2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 32):
    if k1[i]:
        mem.d[i] = zmm2.d[i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQU32, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VINSERTPS
• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS

All 686 AVX10.1 instructions