VMOVDQU64

VMOVDQU64 is the quadword member of the four EVEX encodings of the unaligned integer move: a load, store or register copy of 16, 32 or 64 bytes at any address, with a write mask that selects quadwords. Like VMOVDQU32, whose page covers the pair, it needs only AVX512F (or AVX10.1); VMOVDQU8 shows the masked loads and stores at the end of a buffer, whose left-out elements raise no fault.

A quadword mask is short: bits 7:0 for a zmm register, 3:0 for ymm and 1:0 for xmm, the rest of the mask register ignored. On Zen 5, vmovdqu64 zmm1{k6}, [mem] with A4h in the low byte of K6 loaded quadwords 2, 5 and 7 and kept the other five. With 00b in the two low bits, vmovdqu64 xmm0{k1}{z}, [mem] left all of ZMM0 zero, and the store vmovdqu64 [mem]{k6}, xmm5 wrote nothing.

Which move the compilers name#

At -O2 with -march=x86-64-v4, GCC 14 names its 512-bit integer moves after the element type: VMOVDQU8 in a loop over uint8_t, VMOVDQU32 over int and VMOVDQU64 over int64_t, as in a[i] = b[i] + c[i]. Where no type is known it takes VMOVDQU64: for _mm512_loadu_si512 and _mm512_storeu_si512, a 64-byte structure assignment, and a 256-byte memcpy, four loads and four stores. Clang 23 copies with VMOVUPS, and on ymm registers for the structure and the memcpy, and keeps loops at 256 bits with VEX VMOVDQU.

Masked, they agree: _mm512_maskz_loadu_epi64 and _mm512_mask_storeu_epi64 under a tail mask made with BZHI of FFh compile to vmovdqu64 zmm0{k1}{z}, [rsi] and vmovdqu64 [rdi]{k1}, zmm0 in both. For an 8-bit mask passed as an argument, GCC loads K1 with KMOVB and Clang with KMOVD.

AMD’s latency spreadsheet for Zen 5 lists VMOVDQU64 as one macro-op on any of the four vector pipes and notes that without a mask the forms are a plain load, a plain store or a register move that can be eliminated. Zen 5’s 9 recorded cases cover every form, masked and zeroing.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = src2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:
        mem.q[i] = zmm2.q[i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQU64, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VMAXPD
• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW

All 686 AVX10.1 instructions