x86-64.net

Instruction

VMOVDQU64

Moves integer vectors between registers and memory without an alignment requirement, masked at quadword granularity.

Extensions
Forms
9 (9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVDQU64 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVDQU64 zmm {k}{z}, zmm VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512EVEX.512.F3.0F.W1 6F /r
EVEX.512.F3.0F.W1 7F /r		AVX10.1 or AVX512F
VMOVDQU64 zmm {k}{z}, m512 VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512EVEX.512.F3.0F.W1 6F /rAVX10.1 or AVX512F
VMOVDQU64 m512 {k}, zmm VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512EVEX.512.F3.0F.W1 7F /rAVX10.1 or AVX512F
VMOVDQU64 xmm {k}{z}, xmm VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512EVEX.128.F3.0F.W1 6F /r
EVEX.128.F3.0F.W1 7F /r		AVX10.1 or AVX512F + AVX512VL
VMOVDQU64 xmm {k}{z}, m128 VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512EVEX.128.F3.0F.W1 6F /rAVX10.1 or AVX512F + AVX512VL
VMOVDQU64 m128 {k}, xmm VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512EVEX.128.F3.0F.W1 7F /rAVX10.1 or AVX512F + AVX512VL
VMOVDQU64 ymm {k}{z}, ymm VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512EVEX.256.F3.0F.W1 6F /r
EVEX.256.F3.0F.W1 7F /r		AVX10.1 or AVX512F + AVX512VL
VMOVDQU64 ymm {k}{z}, m256 VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512EVEX.256.F3.0F.W1 6F /rAVX10.1 or AVX512F + AVX512VL
VMOVDQU64 m256 {k}, ymm VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512EVEX.256.F3.0F.W1 7F /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQU64, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mask_loadu_epi64 __m128i _mm_mask_loadu_epi64(__m128i __W, __mmask8 __U, const void *__P)

VMOVDQU64 xmm {k}, m128 EVEX.128 -mavx512vl

_mm_mask_storeu_epi64 void _mm_mask_storeu_epi64(void *__P, __mmask8 __U, __m128i __A)

VMOVDQU64 m128 {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_loadu_epi64 __m128i _mm_maskz_loadu_epi64(__mmask8 __U, const void *__P)

VMOVDQU64 xmm {k}{z}, m128 EVEX.128 -mavx512vl

_mm256_mask_loadu_epi64 __m256i _mm256_mask_loadu_epi64(__m256i __W, __mmask8 __U, const void *__P)

VMOVDQU64 ymm {k}, m256 EVEX.256 -mavx512vl

_mm256_mask_storeu_epi64 void _mm256_mask_storeu_epi64(void *__P, __mmask8 __U, __m256i __A)

VMOVDQU64 m256 {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_loadu_epi64 __m256i _mm256_maskz_loadu_epi64(__mmask8 __U, const void *__P)

VMOVDQU64 ymm {k}{z}, m256 EVEX.256 -mavx512vl

_mm512_loadu_epi64 __m512i _mm512_loadu_epi64(const void *__P)

VMOVDQU64 zmm, m512 EVEX.512 -mavx512f

_mm512_loadu_si512 __m512i _mm512_loadu_si512(const void *__P)

VMOVDQU64 zmm, m512 EVEX.512 -mavx512f

_mm512_storeu_epi64 void _mm512_storeu_epi64(void *__P, __m512i __A)

VMOVDQU64 m512, zmm EVEX.512 -mavx512f

_mm512_storeu_si512 void _mm512_storeu_si512(void *__P, __m512i __A)

VMOVDQU64 m512, zmm EVEX.512 -mavx512f

_mm512_mask_loadu_epi64 __m512i _mm512_mask_loadu_epi64(__m512i __W, __mmask8 __U, const void *__P)

VMOVDQU64 zmm {k}, m512 EVEX.512 -mavx512f

_mm512_mask_storeu_epi64 void _mm512_mask_storeu_epi64(void *__P, __mmask8 __U, __m512i __A)

VMOVDQU64 m512 {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_loadu_epi64 __m512i _mm512_maskz_loadu_epi64(__mmask8 __U, const void *__P)

VMOVDQU64 zmm {k}{z}, m512 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.