VMOVDQU8

VMOVDQU8 is the masked load and store of AVX512BW at byte granularity: each bit of the mask register decides whether one byte moves. Without a mask it moves the whole vector at any address, as VMOVDQU does in VEX. The EVEX encodings of that move all carry an element size in their names, which matters only for masking: VMOVDQU16, VMOVDQU32 and VMOVDQU64 mask words, doublewords and quadwords. The mask field cannot name K0, since that encoding means no mask.

Its main use is the end of a buffer. A loop that handles 64 bytes at a time can take the last n bytes with a mask of the n low bits, made with BZHI from all ones and moved to a mask register with KMOVQ, instead of finishing in a scalar loop. GCC 14 and Clang 23 at -O2 compile _mm512_maskz_loadu_epi8 and _mm512_mask_storeu_epi8 with such a mask that way.

• A masked load takes only the selected bytes, and faults on the others are suppressed, so the load may reach past the end of the buffer into an unmapped page. With {z} the other bytes of the register become zero; without it they keep their old values, which makes the instruction depend on the register’s previous contents.
• A masked store writes only the selected bytes and leaves the rest of memory untouched. Stores take no {z}.
• Between registers, the merging form is a byte blend, which both compilers emit for _mm512_mask_blend_epi8 when one input may be overwritten; VPBLENDMB writes the blend to a third register.

The vendors’ guides add costs to weigh. Intel’s describes this kind of remainder masking and warns that a load from the address of a recent masked store whose mask is neither all ones nor all zeros cannot take its data from the store, and waits until the store has reached the cache. AMD’s Zen 5 guide notes that merge masking reads the destination as an extra source and may add latency or reduce throughput.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:
        zmm1.b[i] = src2.b[i]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 8):
    if k1[i]:
        mem.b[i] = zmm2.b[i]
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVDQU8, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VMAXPH
• VMAXPS
• VMAXSD
• VMAXSH
• VMAXSS
• VMINPD
• VMINPH
• VMINPS
• VMINSD
• VMINSH
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD

All 686 AVX10.1 instructions