VMOVHLPS instruction (AVX, AVX10.1)

VMOVHLPS is the VEX and EVEX form of MOVHLPS, whose page covers folding a vector in half for a horizontal sum. The legacy form moves the high quadword of its source into the low quadword of the destination and keeps the destination’s own high quadword. The three-operand form keeps nothing of the destination: the low quadword comes from the high quadword of the last operand, the high quadword from the high quadword of the first source, and bits 128 and up are cleared. With one register as both sources, vmovhlps xmm1, xmm0, xmm0 puts the upper pair of XMM0 in both halves of XMM1, which is all a sum needs. Only the 128-bit register form exists: VEX.L or EVEX.L’L set raises #UD, and with a memory operand the same opcode is VMOVLPS. The VEX form needs AVX; the EVEX form, AVX-512F or AVX10.1, reaches XMM16 to XMM31 but takes no write mask.

On Zen 5, vmovhlps xmm0, xmm13, xmm9 put the high quadword of XMM9 below the high quadword of XMM13 and cleared bits 511:128 of ZMM0, and {evex} vmovhlps xmm1, xmm2, xmm3 did the same with XMM3 and XMM2.

Folding without a copy

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 compiles _mm_movehl_ps(a, b) to vmovhlps xmm0, xmm0, xmm1, and the sum of four floats from MOVHLPS’s page to vmovhlps xmm1, xmm0, xmm0 and VADDPS: the MOVAPS copy that the legacy form needed is gone, since the separate destination leaves v intact for the addition. The sum of a __m256 first adds its two halves after VEXTRACTF128, VEXTRACTF32X4 in GCC at -v4, and then folds the same way. Clang 23 writes the intrinsic as vunpckhpd xmm0, xmm1, xmm0 and folds with VSHUFPD and immediate 1, which move the same 64 bits.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows alike one macro-op on pipes FP0 to FP3, a latency of 1 cycle and four per cycle. VMOVLHPS moves the other way.

Forms

Every encoding of VMOVHLPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVHLPS xmm, xmm, xmm` VMOVHLPS_XMMdq_XMMdq_XMMdq	`VEX.128.NP.0F.WIG 12 /r`	AVX
`VMOVHLPS xmm, xmm, xmm` VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512	`EVEX.128.NP.0F.W0 12 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, xmm`
Sandy Bridge, Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids	1 / 1p5
Lunar Lake	1 / 0.5V2 V3
Piledriver	2 / 1FPFMA FPU0 FPU1
Zen, Zen 2	1 / 0.5FPU1 FPU2
Zen 3, Zen 4	1 / 0.5FP1 FP2
Jaguar	1 / 0.5FPA FPM FPU0 FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The high quadword of xmm3 becomes the low quadword of the result; the high quadword comes from xmm2.

Result quadwords 1 to 0: a1, b1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.q[0] = xmm3.q[1]
xmm1.q[1] = xmm2.q[1]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVHLPS xmm, xmm, xmm`
`xmm`	explicit	write
`xmm`	explicit	read
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-7
EVEX forms: AVX512-E7NM128

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Folding without a copy#