Extensions
Forms
2 (1 VEX, 1 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVHLPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVHLPS xmm, xmm, xmm VMOVHLPS_XMMdq_XMMdq_XMMdqVEX.128.NP.0F.WIG 12 /rAVX
VMOVHLPS xmm, xmm, xmm VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512EVEX.128.NP.0F.W0 12 /rAVX10.1 or AVX512F

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.