VMOVHPD instruction (AVX, AVX10.1)

VMOVHPD is the VEX and EVEX form of MOVHPD, whose page covers gathering two doubles from different addresses and AMD’s advice against loading registers in halves. The store is unchanged: it writes the high double of an XMM register to eight bytes of memory. The load gains a source: the low double comes from the first source register, the high one from memory, and bits 128 and up are zeroed. Only 128-bit forms exist: VEX.L or EVEX.L’L asking for more, or a store whose vvvv field is not 1111b, raises #UD. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1, which reaches XMM16 to XMM31 but takes no mask. VMOVHPS does the same with no 66 prefix.

On Zen 5, vmovhpd xmm12, xmm6, qword ptr [mem] took the low double of XMM6 and the eight bytes from memory and cleared bits 511:128 of ZMM12, and {evex} vmovhpd xmm24, xmm3, qword ptr [mem] did the same with XMM3. Both stores, VEX and EVEX, wrote the high double of XMM1 and left the next bytes alone.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or x86-64-v4, GCC 14 compiles _mm_loadh_pd, v[1] = *p on a __m128d and _mm_storeh_pd to VMOVHPD, and (__m128d){*p, *q} to VMOVSD and VMOVHPD; for four doubles from four addresses it builds two such halves and joins them with VINSERTF128 (VINSERTF64X2 at -v4). Clang 23 writes the same code with VMOVHPS, as on VMOVHPS’s page. Neither compiler uses VMOVHPD for the loop of MOVHPD’s page that interleaves two arrays of doubles: GCC permutes whole ymm registers with VPERMPD and VSHUFPD at -v3 and uses VPERMT2PD at -v4.

AMD’s latency spreadsheet for Zen 5 gives the load one macro-op, two per cycle, with a latency of 1 cycle, and the store two macro-ops, two per cycle; its EVEX row gives the store a latency of 2 cycles, where the VEX row gives none.

Forms

Every encoding of VMOVHPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVHPD xmm, xmm, m64` VMOVHPD_XMMdq_XMMq_MEMq	`VEX.128.66.0F.WIG 16 /r`	AVX
`VMOVHPD m64, xmm` VMOVHPD_MEMq_XMMdq	`VEX.128.66.0F.WIG 17 /r`	AVX
`VMOVHPD xmm, xmm, m64` VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512	`EVEX.128.66.0F.W1 16 /r`	AVX10.1 or AVX512F
`VMOVHPD m64, xmm` VMOVHPD_MEMf64_XMMf64_AVX512	`EVEX.128.66.0F.W1 17 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m64`	`m64, xmm`	`xmm, xmm, m64`	`m64, xmm`
Sandy Bridge	7 / 1p5	1 / 1p4 p23
Haswell, Broadwell, Skylake	6 / 1p5	1 / 1p2347
Skylake-SP	6 / 1p5	1 / 1p2347	7 / 1p5	1 / 1p2347
Ice Lake	7 / 1p5	1 / 0.5p4789	7 / 0.5p15	1 / 0.5p4789
Alder Lake	8 / 1p5	12 / 0.5p4789
Sapphire Rapids	8 / 1p5	12 / 0.5p4789	8 / 1p5	12 / 0.5p4789
Lunar Lake	8 / 0.5V2 V3	12 / 0.5p10 p11 p25 p26 p27
Piledriver	7 / 1.5FPFMA FPU0 FPU1	2 / 1.5AGLU01 FPSTO FPU2 FPU3 Store
Zen	8 / 0.5FPU1 FPU2	1 / 0.5AGU0 AGU1
Zen 2	8 / 0.5FPU1 FPU2	1 / 0.33AGU0 AGU1 AGU2
Zen 3	8 / 0.5FP1 FP2	2 / 1FP45 FPSt LSU Store
Zen 4	8 / 0.5FP1 FP2	2 / 1FP45 FPSt LSU Store	8 / 0.5FP1 FP2	1 / 1FP45 FPSt LSU Store
Jaguar	6 / 1FPA FPM FPU0 FPU1	2 / 1FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the high half: m64 becomes the high quadword of the result; the other quadword comes from xmm2.VMOVHPD xmm, xmm, m64

Result quadwords 1 to 0: b0, a0.

A store of the high half: quadword 1 of xmm2 goes to m64.VMOVHPD m64, xmm

m64 receives quadword 1 of xmm2: a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VMOVHPD xmm, xmm, m64

xmm1.q[1] = mem.q[0]
xmm1.q[0] = xmm2.q[0]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

VMOVHPD m64, xmm

mem.q[0] = xmm2.q[1]

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVHPD xmm, xmm, m64`
`xmm`	explicit	write
`xmm`	explicit	read
`m64`	explicit	read
`VMOVHPD m64, xmm`
`m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVHPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadh_pd` `__m128d _mm_loadh_pd(__m128d __a, const double *__dp)`	`VMOVHPD xmm, xmm, m64` VEX.128 -mavxwith AVX enabled
`_mm_loadh_pi` `__m128 _mm_loadh_pi(__m128 __a, const __m64 *__p)`	`VMOVHPD xmm, xmm, m64` VEX.128 -mavxwith AVX enabled
`_mm_storeh_pd` `void _mm_storeh_pd(double *__dp, __m128d __a)`	`VMOVHPD m64, xmm` VEX.128 -mavxwith AVX enabled
`_mm_storeh_pi` `void _mm_storeh_pi(__m64 *__p, __m128 __a)`	`VMOVHPD m64, xmm` VEX.128 -mavxwith AVX enabled Clang's comment names VPEXTRQ; this intrinsic stores the upper half of a vector to memory, and Clang emits MOVHPD or VMOVHPD.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#