x86-64.net

Instruction

VMOVHPS

Loads two singles from memory into the high half of an XMM register, or stores the high two to memory.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVHPS xmm, xmm, m64 VMOVHPS_XMMdq_XMMq_MEMqVEX.128.NP.0F.WIG 16 /rAVX
VMOVHPS m64, xmm VMOVHPS_MEMq_XMMdqVEX.128.NP.0F.WIG 17 /rAVX
VMOVHPS xmm, xmm, m64 VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512EVEX.128.NP.0F.W0 16 /rAVX10.1 or AVX512F
VMOVHPS m64, xmm VMOVHPS_MEMf32_XMMf32_AVX512EVEX.128.NP.0F.W0 17 /rAVX10.1 or AVX512F

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.