x86-64.net

Instruction

VMOVHPS

Loads two singles from memory into the high half of an XMM register, or stores the high two to memory.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

VMOVHPS is the VEX and EVEX form of MOVHPS, whose page covers the pairs of floats compilers move with it. The store is unchanged: it writes the high quadword of an XMM register to 8 bytes of memory. The load gains a source: the low quadword comes from the first source register, the high one from memory, and bits 128 and up are zeroed, so the result no longer depends on the destination’s old value. Only 128-bit forms exist: a VEX.L or EVEX.L’L asking for more, or a store whose vvvv field is not 1111b, raises #UD. The VEX form needs AVX, the EVEX form AVX-512F or AVX10.1, which reaches XMM16 to XMM31 but takes no mask. With a register in place of memory the opcode is VMOVLHPS.

On Zen 5, the recorded vmovhps xmm12, xmm6, qword ptr [mem] took the low quadword of XMM6 and the eight bytes from memory and cleared bits 511:128 of ZMM12, and {evex} vmovhps xmm9, xmm9, qword ptr [mem], with one register as source and destination, did what the legacy load does to XMM9 but cleared the bits above. Both stores, VEX and EVEX, wrote only the eight bytes.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or x86-64-v4:

  • _mm_loadh_pi and _mm_storeh_pi are VMOVHPS in GCC 14 and Clang 23, and Clang also compiles _mm_loadh_pd to VMOVHPS, where GCC uses VMOVHPD.
  • (__m128){p[0], p[1], q[0], q[1]} is VMOVSD and VMOVHPS in Clang; GCC loads singles with VMOVSS and VINSERTPS and joins the halves with VMOVLHPS.
  • Storing elements 2 and 3 to two floats is the store form in Clang; GCC shifts with VPSRLDQ and stores with VMOVLPS at -v3, and extracts with VPEXTRQ to a general register at -v4.

AMD’s latency spreadsheet for Zen 5 gives the load one macro-op with a latency of 1 cycle and the store two macro-ops, two per cycle each; its EVEX row gives the store a latency of 2 cycles, where the VEX row has none.

Forms

Every encoding of VMOVHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVHPS xmm, xmm, m64 VMOVHPS_XMMdq_XMMq_MEMqVEX.128.NP.0F.WIG 16 /rAVX
VMOVHPS m64, xmm VMOVHPS_MEMq_XMMdqVEX.128.NP.0F.WIG 17 /rAVX
VMOVHPS xmm, xmm, m64 VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512EVEX.128.NP.0F.W0 16 /rAVX10.1 or AVX512F
VMOVHPS m64, xmm VMOVHPS_MEMf32_XMMf32_AVX512EVEX.128.NP.0F.W0 17 /rAVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m64m64, xmmxmm, xmm, m64m64, xmm
Sandy Bridge7 / 1p51 / 1p4 p23
Haswell, Broadwell, Skylake6 / 1p51 / 1p2347
Skylake-SP6 / 1p51 / 1p23477 / 1p51 / 1p2347
Ice Lake7 / 1p51 / 0.5p47897 / 0.5p151 / 0.5p4789
Alder Lake8 / 1p512 / 0.5p4789
Sapphire Rapids8 / 1p512 / 0.5p47898 / 1p512 / 0.5p4789
Lunar Lake8 / 0.5V2 V312 / 0.5p10 p11 p25 p26 p27
Piledriver7 / 1.5FPFMA FPU0 FPU12 / 1.5AGLU01 FPSTO FPU2 FPU3 Store
Zen8 / 0.5FPU1 FPU21 / 0.5AGU0 AGU1
Zen 28 / 0.5FPU1 FPU21 / 0.33AGU0 AGU1 AGU2
Zen 38 / 0.5FP1 FP22 / 1FP45 FPSt LSU Store
Zen 48 / 0.5FP1 FP22 / 1FP45 FPSt LSU Store8 / 0.5FP1 FP21 / 1FP45 FPSt LSU Store
Jaguar6 / 1FPA FPM FPU0 FPU12 / 1FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the high half: m64 becomes the high quadword of the result; the other quadword comes from xmm2.VMOVHPS xmm, xmm, m64
VMOVHPS: the high half loadedResult quadwords 1 to 0: b0, a0.01xmm2aa0b0xmm10m64b

Result quadwords 1 to 0: b0, a0.

A store of the high half: quadword 1 of xmm2 goes to m64.VMOVHPS m64, xmm
VMOVHPS: the high half storedm64 receives quadword 1 of xmm2: a1.01a1m64

m64 receives quadword 1 of xmm2: a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VMOVHPS xmm, xmm, m64
xmm1.q[1] = mem.q[0]
xmm1.q[0] = xmm2.q[0]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

VMOVHPS m64, xmm
mem.q[0] = xmm2.q[1]

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VMOVHPS xmm, xmm, m64
xmmexplicitwrite
xmmexplicitread
m64explicitread
VMOVHPS m64, xmm
m64explicitwrite
xmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E9NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-76 (MOVHPS)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  6. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  7. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.