VMOVLHPS instruction (AVX, AVX10.1)

VMOVLHPS is the VEX and EVEX form of MOVLHPS, whose page explains why Clang uses it for doubles as a shorter UNPCKLPD. The three-operand form keeps the low quadword of the first source, puts the low quadword of the last operand above it and clears bits 128 and up, where the legacy form kept the destination’s own low half. VMOVHLPS covers what the encodings share: a 128-bit register form only, #UD for VEX.L or EVEX.L’L set, AVX for VEX and AVX-512F or AVX10.1 for EVEX, without a write mask. With a memory operand the opcode is VMOVHPS.

On Zen 5, vmovlhps xmm0, xmm13, xmm9 kept the low quadword of XMM13, placed the low quadword of XMM9 above it and cleared bits 511:128 of ZMM0, and {evex} vmovlhps xmm5, xmm5, xmm5 copied the low quadword of XMM5 into both halves.

The same length as VUNPCKLPD

On xmm registers the result is that of VUNPCKLPD, and in VEX the byte that MOVLHPS saves is gone: the 66 prefix of UNPCKLPD becomes two bits of the VEX prefix, so both instructions have the same length. Clang 23 keeps its habit anyway. In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, it compiles _mm_movelh_ps, _mm_unpacklo_pd(a, b) and _mm_set_pd(b, a) all to vmovlhps xmm0, xmm0, xmm1, while GCC 14 emits VMOVLHPS for the first and VUNPCKLPD for the other two. For _mm_set1_pd(x) both now use VMOVDDUP on the register rather than a move of the register into its own high half. Only the xmm form exists, so for _mm256_unpacklo_pd both compilers emit VUNPCKLPD.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows one macro-op on pipes FP0 to FP3, a latency of 1 cycle and four per cycle, as for VMOVHLPS.

Forms

Every encoding of VMOVLHPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVLHPS xmm, xmm, xmm` VMOVLHPS_XMMdq_XMMq_XMMq	`VEX.128.NP.0F.WIG 16 /r`	AVX
`VMOVLHPS xmm, xmm, xmm` VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512	`EVEX.128.NP.0F.W0 16 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, xmm`
Sandy Bridge, Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids	1 / 1p5
Lunar Lake	1 / 0.5V2 V3
Piledriver	2 / 1FPFMA FPU0 FPU1
Zen, Zen 2	1 / 0.5FPU1 FPU2
Zen 3, Zen 4	1 / 0.5FP1 FP2
Jaguar	1 / 0.5FPA FPM FPU0 FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low quadword of xmm3 becomes the high quadword of the result; the low quadword comes from xmm2.

Result quadwords 1 to 0: b0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.q[0] = xmm2.q[0]
xmm1.q[1] = xmm3.q[0]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVLHPS xmm, xmm, xmm`
`xmm`	explicit	write
`xmm`	explicit	read
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-7
EVEX forms: AVX512-E7NM128

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

The same length as VUNPCKLPD#