x86-64.net

Instruction

VMOVLPD

Loads a double from memory into the low half of an XMM register, or stores the low double to memory.

Extensions
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVLPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVLPD xmm, xmm, m64 VMOVLPD_XMMdq_XMMdq_MEMqVEX.128.66.0F.WIG 12 /rAVX
VMOVLPD m64, xmm VMOVLPD_MEMq_XMMqVEX.128.66.0F.WIG 13 /rAVX
VMOVLPD xmm, xmm, m64 VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512EVEX.128.66.0F.W1 12 /rAVX10.1 or AVX512F
VMOVLPD m64, xmm VMOVLPD_MEMf64_XMMf64_AVX512EVEX.128.66.0F.W1 13 /rAVX10.1 or AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVLPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_loadl_pd __m128d _mm_loadl_pd(__m128d __a, const double *__dp)

VMOVLPD xmm, xmm, m64 VEX.128 -mavxwith AVX enabled

_mm_loadl_pi __m128 _mm_loadl_pi(__m128 __a, const __m64 *__p)

VMOVLPD xmm, xmm, m64 VEX.128 -mavxwith AVX enabled

_mm_storel_pd void _mm_storel_pd(double *__dp, __m128d __a)

VMOVLPD m64, xmm VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_128N

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.