VMOVLPD instruction (AVX, AVX10.1)

VMOVLPD is the VEX and EVEX form of MOVLPD, whose page covers the merging load, where compilers use it, and what AMD’s guide says about loading halves and skipping the merge. The store writes the low double of an XMM register to eight bytes, as before. The load takes the high double from the first source register and the low one from memory, and zeroes bits 128 and up: the merge remains, but with a named register, which need not be the destination. Only 128-bit forms exist, with the #UD cases of VMOVHPD; the EVEX form (AVX-512F or AVX10.1) reaches XMM16 to XMM31 and takes no mask. VMOVLPS does the same with no 66 prefix.

On Zen 5, the recorded vmovlpd xmm4, xmm4, qword ptr [mem] replaced the low double of XMM4, kept the high one and cleared bits 511:128, and {evex} vmovlpd xmm24, xmm3, qword ptr [mem] put the eight bytes below the high double of XMM3. The stores vmovlpd qword ptr [mem], xmm8 and {evex} vmovlpd qword ptr [mem], xmm0 wrote eight bytes each and left the next ones alone.

In compiled code

In our builds at -O2 with -march=x86-64-v3 or x86-64-v4, GCC 14 compiles _mm_loadl_pd(a, p) and v[0] = *p on a __m128d to vmovlpd xmm0, xmm0, qword ptr [rdi], and _mm_storel_pd to the store; Clang 23 uses VMOVLPS for all three. (__m128d){*p, *q} starts with a VMOVSD load in both, which depends on no register.

AMD’s guide for Zen 5 lists the legacy MOVLPD xmm, [mem] among the instructions whose merge it can skip when the upper bits are known to be zero (Section 2.11.5); VMOVLPD, whose merge comes from a named register, is not in that list. Its latency spreadsheet gives VMOVLPD, load or store, one macro-op on pipes FP0 to FP3, two per cycle, with a latency of 1 cycle, in its VEX and EVEX rows alike.

Forms

Every encoding of VMOVLPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVLPD xmm, xmm, m64` VMOVLPD_XMMdq_XMMdq_MEMq	`VEX.128.66.0F.WIG 12 /r`	AVX
`VMOVLPD m64, xmm` VMOVLPD_MEMq_XMMq	`VEX.128.66.0F.WIG 13 /r`	AVX
`VMOVLPD xmm, xmm, m64` VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512	`EVEX.128.66.0F.W1 12 /r`	AVX10.1 or AVX512F
`VMOVLPD m64, xmm` VMOVLPD_MEMf64_XMMf64_AVX512	`EVEX.128.66.0F.W1 13 /r`	AVX10.1 or AVX512F

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m64`	`m64, xmm`	`xmm, xmm, m64`
Sandy Bridge	7 / 1p5	1 / 1p4 p23
Haswell, Broadwell, Skylake	6 / 1p5	1 / 1p2347
Skylake-SP	6 / 1p5	1 / 1p2347	7 / 1p5
Ice Lake	7 / 1p5	1 / 0.5p4789	7 / 0.5p15
Alder Lake	8 / 0.5p15	12 / 0.5p4789
Sapphire Rapids	8 / 0.5p15	12 / 0.5p4789	8 / 0.5p15
Lunar Lake	8 / 0.33V0 V1 V2 V3	12 / 0.5p10 p11 p25 p26 p27
Piledriver	7 / 1.5FPFMA FPU0 FPU1	2 / 1.5AGLU01 FPSTO FPU2 FPU3 Store
Zen	8 / 0.5FPU1 FPU2	1 / 0.5AGU0 AGU1
Zen 2	8 / 0.5FPU1 FPU2	1 / 0.33AGU0 AGU1 AGU2
Zen 3	8 / 0.5FP1 FP2	1 / 1FP45 FPSt LSU Store
Zen 4	8 / 0.5FP1 FP2	1 / 1FP45 FPSt LSU Store	8 / 0.5FP1 FP2
Jaguar	6 / 1FPA FPM FPU0 FPU1	2 / 1FPU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A load of the low half: m64 becomes the low quadword of the result; the other quadword comes from xmm2.VMOVLPD xmm, xmm, m64

Result quadwords 1 to 0: a1, b0.

A store of the low half: quadword 0 of xmm2 goes to m64.VMOVLPD m64, xmm

m64 receives quadword 0 of xmm2: a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VMOVLPD xmm, xmm, m64

xmm1.q[0] = mem.q[0]
xmm1.q[1] = xmm2.q[1]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 2 cases.

VMOVLPD m64, xmm

mem.q[0] = xmm2.q[0]

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVLPD xmm, xmm, m64`
`xmm`	explicit	write
`xmm`	explicit	read
`m64`	explicit	read
`VMOVLPD m64, xmm`
`m64`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVLPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadl_pd` `__m128d _mm_loadl_pd(__m128d __a, const double *__dp)`	`VMOVLPD xmm, xmm, m64` VEX.128 -mavxwith AVX enabled
`_mm_loadl_pi` `__m128 _mm_loadl_pi(__m128 __a, const __m64 *__p)`	`VMOVLPD xmm, xmm, m64` VEX.128 -mavxwith AVX enabled
`_mm_storel_pd` `void _mm_storel_pd(double *__dp, __m128d __a)`	`VMOVLPD m64, xmm` VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512F_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#