x86-64.net

Instruction

VMOVNTDQ

Stores an integer vector to aligned memory with a non-temporal hint that avoids polluting the caches.

Extensions
Forms
5 (2 VEX, 3 EVEX)
Data
Intel XED v2026.08.23

VMOVNTDQ is the VEX and EVEX form of MOVNTDQ, whose page covers the non-temporal hint, the fencing and the whole-line rule; VMOVNTPS covers what the newer encodings keep: the address aligned to the store’s size, 16, 32 or 64 bytes, on pain of #GP, and no write mask or broadcast in the EVEX forms. The 32-byte VEX form needs only AVX, although it stores integers, while the 32-byte form of its loading partner VMOVNTDQA needs AVX2. The EVEX forms need AVX512F (with AVX512VL below 512 bits) or AVX10.1.

On Zen 5, the five recorded forms each stored their 16, 32 or 64 bytes at an aligned address and left the rest of the buffer alone, among them vmovntdq ymmword ptr [mem], ymm12, the VEX.256 form that Intel’s entry also forbids by asking for VEX.L = 0, as MOVNTDQ’s page notes.

In compiled code

In our builds at -O2 with -march=x86-64-v3, GCC 14 compiles _mm256_stream_si256 to VMOVNTDQ, and _mm512_stream_si512 at -march=x86-64-v4. Clang 23 writes VMOVNTPS for either intrinsic on its own, but VMOVNTDQ in a loop that fills an int array with a value made by the integer VPBROADCASTD. Neither compiler puts an SFENCE after such a loop unless the source calls _mm_sfence().

AMD’s latency spreadsheet for Zen 5 gives the VEX row and the EVEX row one macro-op on pipe FP4 or FP5, two per cycle.

In the optimization guide

What the optimization guide says about VMOVNTDQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

  • Non-temporal stores and fences: Non-temporal stores skip reading the line and write around the caches through write-combining buffers, with weak ordering.
  • Non-temporal stores and fences: Non-temporal stores reach full bandwidth only when they write whole 64-byte lines, and the cores have 8 to 12 write-combining buffers for them.

Forms

Every encoding of VMOVNTDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVNTDQ m128, xmm VMOVNTDQ_MEMdq_XMMdqVEX.128.66.0F.WIG E7 /rAVX
VMOVNTDQ m256, ymm VMOVNTDQ_MEMqq_YMMqqVEX.256.66.0F.WIG E7 /rAVX
VMOVNTDQ m512, zmm VMOVNTDQ_MEMu32_ZMMu32_AVX512EVEX.512.66.0F.W0 E7 /rAVX10.1 or AVX512F
VMOVNTDQ m128, xmm VMOVNTDQ_MEMu32_XMMu32_AVX512EVEX.128.66.0F.W0 E7 /rAVX10.1 or AVX512F + AVX512VL
VMOVNTDQ m256, ymm VMOVNTDQ_MEMu32_YMMu32_AVX512EVEX.256.66.0F.W0 E7 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelm128, xmmm256, ymmm512, zmmm128, xmmm256, ymm
Sandy Bridge1 / 1p4 p231 / 1p4 p23
Haswell, Broadwell, Skylake1 / 1p23471 / 1p2347
Skylake-SP1 / 1p23471 / 1p23471 / 1p23471 / 1p23471 / 1p2347
Ice Lake1 / 0.5p47891 / 0.5p47891 / 0.5p47891 / 0.5p47891 / 0.5p4789
Alder Lake521 / 0.5p4789507 / 0.5p4789
Sapphire Rapids521 / 0.5p4789507 / 0.5p4789473 / 0.5p4789477 / 0.5p4789470 / 0.5p4789
Lunar Lake521 / 0.5p10 p11 p25 p26 p27507 / 0.5p10 p11 p25 p26 p27
Piledriver, Jaguar2 / 1FPU12 / 2FPU1
Zen1 / 0.5AGU0 AGU11 / 0.5AGU0 AGU1
Zen 21 / 0.33AGU0 AGU1 AGU21 / 0.33AGU0 AGU1 AGU2
Zen 31 / 1FP45 FPSt LSU Store1 / 1FP45 FPSt LSU Store
Zen 41 / 1FP45 FPSt LSU Store1 / 1FP45 FPSt LSU Store1 / 1FP45 FPSt LSU Store1 / 1FP45 FPSt LSU Store1 / 1FP45 FPSt LSU Store

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each doubleword is copied to the same place.
VMOVNTDQ: element by elementResult doubleword i is doubleword i of xmm2. Result doublewords 3 to 0: a3, a2, a1, a0.0123xmm2aa0a1a2a3m128

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms.

Result doubleword i is doubleword i of xmm2. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

mem.write(zmm2.read())

Run on AMD Zen 5 (EPYC 9645): 5 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VMOVNTDQ m128, xmm VMOVNTDQ m256, ymm VMOVNTDQ m512, zmm
m128/256/512explicitwrite
xmm, ymm, zmmexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-1
EVEX forms
AVX512-E1NF

Attributes

What else XED records about the forms. How to read.

All forms
aligned memory operand; non-temporal hint; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVNTDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm256_stream_si256 void _mm256_stream_si256(void *__a, __m256i __b)

VMOVNTDQ m256, ymm VEX.256 -mavx

_mm512_stream_si512 void _mm512_stream_si512(void *__P, __m512i __A)

VMOVNTDQ m512, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-88 (MOVNTDQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.