VMOVNTDQA instruction (AVX, AVX2, AVX10.1)

VMOVNTDQA is the VEX and EVEX form of MOVNTDQA, whose page covers the streaming-load hint, what it does on write-combining and on write-back memory, and the fencing. The new forms only change the width and the register: 16 bytes for VEX.128, which needs AVX, 32 for VEX.256, which needs AVX2, and 16, 32 or 64 bytes for EVEX, which needs AVX512F (with AVX512VL below 512 bits) or AVX10.1. Each needs an address aligned to its size, on pain of #GP, and clears the register above what it loads, where the legacy form keeps bits 128 and up. The EVEX forms take no write mask and no broadcast, like the stores of VMOVNTDQ.

On Zen 5, the five recorded forms each loaded their 16, 32 or 64 aligned bytes and zeroed the rest of the ZMM register, the VEX.128 and EVEX.128 forms alike.

In compiled code

In our builds at -O2 with -march=x86-64-v3, GCC 14 and Clang 23 compile _mm256_stream_load_si256 to VMOVNTDQA, and _mm512_stream_load_si512 at -march=x86-64-v4 to the EVEX form. Neither folds the load into the instruction that uses it: adding the result with VPADDD takes a separate VMOVNTDQA into a spare register, since VPADDD’s own memory operand would be an ordinary load. A loop that only copies an array of __m256i through the intrinsic keeps its VMOVNTDQA in GCC, but Clang turns the whole loop into a call to memcpy, and the hint is gone. Clang’s __builtin_nontemporal_load on int elements gives plain MOVs and no vector loop at all.

AMD’s latency spreadsheet for Zen 5 gives the VEX and the EVEX rows one macro-op and two per cycle, as for MOVNTDQA, with no pipe named.

Forms

Every encoding of VMOVNTDQA that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVNTDQA xmm, m128` VMOVNTDQA_XMMdq_MEMdq	`VEX.128.66.0F38.WIG 2A /r`	AVX
`VMOVNTDQA ymm, m256` VMOVNTDQA_YMMqq_MEMqq	`VEX.256.66.0F38.WIG 2A /r`	AVX2
`VMOVNTDQA zmm, m512` VMOVNTDQA_ZMMu32_MEMu32_AVX512	`EVEX.512.66.0F38.W0 2A /r`	AVX10.1 or AVX512F
`VMOVNTDQA xmm, m128` VMOVNTDQA_XMMu32_MEMu32_AVX512	`EVEX.128.66.0F38.W0 2A /r`	AVX10.1 or AVX512F + AVX512VL
`VMOVNTDQA ymm, m256` VMOVNTDQA_YMMu32_MEMu32_AVX512	`EVEX.256.66.0F38.W0 2A /r`	AVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, m128`	`ymm, m256` `zmm, m512`
Sandy Bridge	6 / 0.5p23
Haswell	6 / 0.5p23	7 / 0.5p23
Broadwell	5 / 0.5p23	6 / 0.5p23
Skylake, Skylake-SP, Ice Lake	7 / 0.5p015	8 / 0.5p015
Alder Lake, Sapphire Rapids	7 / 0.33p2 p3 p10	8 / 0.33p2 p3 p10
Lunar Lake	7 / 0.33p20 p21 p22	8 / 0.33p20 p21 p22
Piledriver	5 / 2FPMAL FPU0 FPU1
Zen	8 / 0.5AGU0 AGU1	8 / 0.5AGU0 AGU1
Zen 2	8 / 0.33AGU0 AGU1 AGU2	8 / 0.33AGU0 AGU1 AGU2
Zen 3, Zen 4	8 / 0.5FP45 LSU Load	8 / 0.5FP45 LSU Load
Jaguar	5 / 1FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A move: each doubleword is copied to the same place.

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms.

Result doubleword i is doubleword i of m128. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

zmm1.write(mem.read())
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 5 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVNTDQA xmm, m128` `VMOVNTDQA ymm, m256` `VMOVNTDQA zmm, m512`
`xmm, ymm, zmm`	explicit	write
`m128/256/512`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-1
EVEX forms: AVX512-E1NF

Attributes

What else XED records about the forms. How to read.

All forms: aligned memory operand; non-temporal hint; may abort a TSX transaction

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVNTDQA, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_stream_load_si128` `__m128i _mm_stream_load_si128(const void *__V)`	`VMOVNTDQA xmm, m128` VEX.128 -mavxwith AVX enabled
`_mm256_stream_load_si256` `__m256i _mm256_stream_load_si256(const void *__V)`	`VMOVNTDQA ymm, m256` VEX.256 -mavx2
`_mm512_stream_load_si512` `__m512i _mm512_stream_load_si512(const void *__P)`	`VMOVNTDQA zmm, m512` EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512F_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
`AVX512F_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512F + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[16]` AVX512F `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512F_256` AVX10.1	Same as `AVX512F_128`	Same as `AVX512F_128`

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#