Instruction
VMOVQ
Moves a quadword between an XMM register and a general-purpose register, memory or another XMM register, zeroing the rest of a vector destination.
- Extensions
- Forms
- 13 (8 VEX, 5 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMOVQ xmm, m64 64-bit mode only
VMOVQ_XMMdq_MEMq_6E | VEX.128.66.0F.W1 6E /r | AVX |
VMOVQ m64, xmm 64-bit mode only
VMOVQ_MEMq_XMMq_7E | VEX.128.66.0F.W1 7E /r | AVX |
VMOVQ xmm, m64
VMOVQ_XMMdq_MEMq_7E | VEX.128.F3.0F.WIG 7E /r | AVX |
VMOVQ m64, xmm
VMOVQ_MEMq_XMMq_D6 | VEX.128.66.0F.WIG D6 /r | AVX |
VMOVQ xmm, r64 64-bit mode only
VMOVQ_XMMdq_GPR64q | VEX.128.66.0F.W1 6E /r | AVX |
VMOVQ r64, xmm 64-bit mode only
VMOVQ_GPR64q_XMMq | VEX.128.66.0F.W1 7E /r | AVX |
VMOVQ xmm, xmm
VMOVQ_XMMdq_XMMq_7E | VEX.128.F3.0F.WIG 7E /r | AVX |
VMOVQ xmm, xmm
VMOVQ_XMMdq_XMMq_D6 | VEX.128.66.0F.WIG D6 /r | AVX |
VMOVQ xmm, r64 64-bit mode only
VMOVQ_XMMu64_GPR64u64_AVX512 | EVEX.128.66.0F.W1 6E /r | AVX10.1 or AVX512F |
VMOVQ xmm, m64
VMOVQ_XMMu64_MEMu64_AVX512 | EVEX.128.66.0F.W1 6E /rEVEX.128.F3.0F.W1 7E /r | AVX10.1 or AVX512F |
VMOVQ r64, xmm 64-bit mode only
VMOVQ_GPR64u64_XMMu64_AVX512 | EVEX.128.66.0F.W1 7E /r | AVX10.1 or AVX512F |
VMOVQ m64, xmm
VMOVQ_MEMu64_XMMu64_AVX512 | EVEX.128.66.0F.W1 7E /rEVEX.128.66.0F.W1 D6 /r | AVX10.1 or AVX512F |
VMOVQ xmm, xmm
VMOVQ_XMMu64_XMMu64_AVX512 | EVEX.128.F3.0F.W1 7E /rEVEX.128.66.0F.W1 D6 /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMOVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtsi128_si64
long long _mm_cvtsi128_si64(__m128i __a) |
|
_mm_cvtsi64_si128
__m128i _mm_cvtsi64_si128(long long __a) |
|
_mm_loadl_epi64
__m128i _mm_loadl_epi64(const __m128i_u *__p) |
|
_mm_loadu_si64
__m128i _mm_loadu_si64(const void *__a) |
|
_mm_move_epi64
__m128i _mm_move_epi64(__m128i __a) |
|
_mm_set_sd
__m128d _mm_set_sd(double __w) |
|
_mm_storeu_si64
void _mm_storeu_si64(void *__p, __m128i __b) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_128N | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.