VMOVQ

VMOVQ is the VEX and EVEX form of MOVQ, whose page explains its three kinds of opcode and the compilers’ choices among them. All carry over: 66 0F 6E and 7E with W1 to and from a general-purpose register or memory, F3 0F 7E into an XMM register and 66 0F D6 out of one. Into a register, the newer encodings zero every bit above 63. Only 128-bit forms exist, and VEX.L = 1 raises #UD. The VEX form needs AVX; the EVEX form, AVX-512F or AVX10.1, adds XMM16 to XMM31 and no mask.

The W bit#

VEX ignores W in the F3 0F 7E and 66 0F D6 forms, but EVEX asks for W1 there: with W0, AVX10.2 makes them VMOVD between XMM registers. In the 6E and 7E forms W picks the size, and Intel’s table notes that outside 64-bit mode W1 is ignored, so 32-bit code moving 64 bits uses the F3 0F 7E and 66 0F D6 forms. In our builds, GNU as 2.44 encodes vmovq xmm0, qword ptr [rdi] as F3 0F 7E; the W1 6E and 7E memory forms, recorded on Zen 5 through .insn, moved the same eight bytes.

Also on Zen 5, {store} vmovq xmm4, xmm4, the D6 form between registers, kept the low quadword and cleared bits 511:64 of ZMM4, and {store} {evex} vmovq rax, xmm17 copied XMM17’s low quadword, 2C1F1205F8EBDED1h, to RAX.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 or x86-64-v4, GCC 14 and Clang 23 emit VMOVQ where MOVQ’s page shows MOVQ, vmovq xmm0, xmm0 for _mm_move_epi64 included. Clang relies on the zeroing: for _mm256_zextsi128_si256(_mm_loadl_epi64(p)) it emits one VMOVSD, while GCC loads with VMOVQ and adds a vmovdqa xmm0, xmm0. For _mm256_set1_epi64x(x) both use VMOVQ and VPBROADCASTQ at -v3, and at -v4 VPBROADCASTQ alone, which reads RDI itself.

AMD’s latency spreadsheet for Zen 5 gives VMOVQ from a general-purpose register one macro-op in its VEX and EVEX rows, against two for legacy MOVQ, and a copy between XMM registers one cycle, four per cycle, in its VEX row.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(src2.q[0])  # zeroed from bit 64 up

dest.write(xmm2.q[0])

xmm1.write(xmm2.q[0])  # zeroed from bit 64 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMINSD
• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB

All 253 AVX instructions

More AVX10.1 instructions

• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW

All 686 AVX10.1 instructions