VMOVRSB instruction (MOVRS)

VMOVRSB is the byte-masked form of VMOVRSD: it loads 16, 32 or 64 bytes into an XMM, YMM or ZMM register with the read-shared hint, and each mask bit decides one byte. Bytes left out keep the destination’s value under merging masking or become zero with {z}, and raise no fault in memory, as a masked VMOVDQU8 load does. Unmasked it loads the same bits as VMOVRSD.

The VMOVRSD page says what the hint asks of the caches, and that a load of this kind gives the same data as an ordinary one. It needs the MOVRS bit, CPUID.(EAX=07H,ECX=1):EAX[31], and AVX10. It shares EVEX opcode 6F of map 5 with its siblings: F2 with W0 selects the bytes.

In our builds, Clang 23 at -O2 with -mavx10.2 -mmovrs compiled _mm512_loadrs_epi8 to vmovrsb zmm0, zmmword ptr [rdi]; GCC 14 has no such option. Zen 5 raised #UD for all three recorded cases.

Forms

Every encoding of VMOVRSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVRSB xmm {k}{z}, m128` 64-bit mode only VMOVRSB_XMMu8_MASKmskw_MEMu8_AVX512	`EVEX.128.F2.MAP5.W0 6F /r`	MOVRS + AVX10
`VMOVRSB ymm {k}{z}, m256` 64-bit mode only VMOVRSB_YMMu8_MASKmskw_MEMu8_AVX512	`EVEX.256.F2.MAP5.W0 6F /r`	MOVRS + AVX10
`VMOVRSB zmm {k}{z}, m512` 64-bit mode only VMOVRSB_ZMMu8_MASKmskw_MEMu8_AVX512	`EVEX.512.F2.MAP5.W0 6F /r`	MOVRS + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A masked move: each byte is copied where its bit of k1 is 1; elsewhere merging keeps the old element, and zeroing writes 0.

merging, {k1}

zeroing, {k1}{z}

Example mask k1 = 0xB2. Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms.

With merging: result bytes 7 to 0: a7, unchanged, a5, a4, unchanged, unchanged, a1, unchanged.

With zeroing: result bytes 7 to 0: a7, 0, a5, a4, 0, 0, a1, 0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 31 & 1:
    fault(UD)  # CPUID: no MOVRS
if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
for i in range(VL // 8):
    if k1[i]:
        zmm1.b[i] = mem.b[i]
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no MOVRS, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVRSB xmm {k}{z}, m128` 64-bit mode only `VMOVRSB ymm {k}{z}, m256` 64-bit mode only `VMOVRSB zmm {k}{z}, m512` 64-bit mode only
`xmm, ymm, zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`m128/256/512`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms: write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVRSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadrs_epi8` `__m128i _mm_loadrs_epi8(const void *__A)`	`VMOVRSB xmm, m128` EVEX.128 -mmovrs -mavx10.2
`_mm_mask_loadrs_epi8` `__m128i _mm_mask_loadrs_epi8(__m128i __W, __mmask16 __U, const void *__A)`	`VMOVRSB xmm {k}, m128` EVEX.128 -mmovrs -mavx10.2
`_mm_maskz_loadrs_epi8` `__m128i _mm_maskz_loadrs_epi8(__mmask16 __U, const void *__A)`	`VMOVRSB xmm {k}{z}, m128` EVEX.128 -mmovrs -mavx10.2
`_mm256_loadrs_epi8` `__m256i _mm256_loadrs_epi8(const void *__A)`	`VMOVRSB ymm, m256` EVEX.256 -mmovrs -mavx10.2
`_mm256_mask_loadrs_epi8` `__m256i _mm256_mask_loadrs_epi8(__m256i __W, __mmask32 __U, const void *__A)`	`VMOVRSB ymm {k}, m256` EVEX.256 -mmovrs -mavx10.2
`_mm256_maskz_loadrs_epi8` `__m256i _mm256_maskz_loadrs_epi8(__mmask32 __U, const void *__A)`	`VMOVRSB ymm {k}{z}, m256` EVEX.256 -mmovrs -mavx10.2
`_mm512_loadrs_epi8` `__m512i _mm512_loadrs_epi8(const void *__A)`	`VMOVRSB zmm, m512` EVEX.512 -mmovrs -mavx10.2
`_mm512_mask_loadrs_epi8` `__m512i _mm512_mask_loadrs_epi8(__m512i __W, __mmask64 __U, const void *__A)`	`VMOVRSB zmm {k}, m512` EVEX.512 -mmovrs -mavx10.2
`_mm512_maskz_loadrs_epi8` `__m512i _mm512_maskz_loadrs_epi8(__mmask64 __U, const void *__A)`	`VMOVRSB zmm {k}{z}, m512` EVEX.512 -mmovrs -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX10_MOVRS_128` MOVRS	MOVRS + AVX10 `CPUID.(EAX=07H,ECX=1):EAX[31]` MOVRS `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	Nova Lake, Diamond Rapids
`AVX10_MOVRS_256` MOVRS	Same as `AVX10_MOVRS_128`	Same as `AVX10_MOVRS_128`
`AVX10_MOVRS_512` MOVRS	Same as `AVX10_MOVRS_128`	Same as `AVX10_MOVRS_128`

VMOVRSB