VMOVRSD

VMOVRSD loads 16, 32 or 64 bytes from memory into an XMM, YMM or ZMM register, as an unaligned VMOVDQU32 load does, and adds a hint that the data will be read by several processors. The bits it loads are the same, with a write mask choosing doublewords. There is no store form and no register source: only the load direction carries the hint.

What the hint asks for#

Intel processors normally treat a first read as private data that may soon be written. Data that many cores read then needs snoops to reach each reader, and that matters most on hardware with a non-inclusive last level cache. On a miss, a read-shared load may change which cache takes the line and in what coherence state, to reduce those snoops. On a hit Intel expects no difference, and the hint is not stored with the line, though hardware prefetchers train on it.

So it suits data shared by many readers and written rarely. A later write still works as usual but may take longer than after an ordinary load, and mixing the two kinds of load on a line gives correct data with less predictable caching. Intel suggests using one kind per access pattern, changing between program phases if sharing changes.

Requirements and siblings#

It needs both the MOVRS bit, CPUID.(EAX=07H,ECX=1):EAX[31], and AVX10. Intel lists MOVRS for Diamond Rapids and Nova Lake. It is in class E4, so masked-out elements raise no fault, and it has no alignment requirement and no broadcast form. Zen 5 raised #UD in all three recorded cases, at each vector length.

VMOVRSB, VMOVRSW and VMOVRSQ differ only in the mask’s granularity, and MOVRS is the general-purpose form. PREFETCHRST2 prefetches with the same hint.

In our builds#

GCC 14 has no -mmovrs. Clang 23 at -O2 with -mavx10.2 -mmovrs compiled _mm512_loadrs_epi32 to vmovrsd zmm0, zmmword ptr [rdi], _mm256_loadrs_epi32 to the YMM form and _mm512_mask_loadrs_epi32 to a KMOVD and vmovrsd zmm0 {k1}, zmmword ptr [rsi].

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 31 & 1:
    fault(UD)  # CPUID: no MOVRS
if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = mem.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVRSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More MOVRS instructions

• MOVRS
• PREFETCHRST2
• VMOVRSB
• VMOVRSQ
• VMOVRSW