VMOVRSW instruction (MOVRS)

VMOVRSW is the word-masked form of VMOVRSD: it loads 16, 32 or 64 bytes into an XMM, YMM or ZMM register with the read-shared hint, and each mask bit decides one word, so 8, 16 or 32 bits of the mask register are used. Words left out keep the destination’s value or become zero with {z}, and raise no fault, as a masked VMOVDQU16 load does. Unmasked it loads the same bits as VMOVRSB and VMOVRSD.

The VMOVRSD page covers the hint, the requirements and the alignment. In the shared opcode, F2 with W1 selects the words. In our builds, Clang 23 at -O2 with -mavx10.2 -mmovrs compiled _mm512_loadrs_epi16 to vmovrsw zmm0, zmmword ptr [rdi]; GCC 14 has no such option. Zen 5 raised #UD for all three recorded cases.

Forms

Every encoding of VMOVRSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVRSW xmm {k}{z}, m128` 64-bit mode only VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512	`EVEX.128.F2.MAP5.W1 6F /r`	MOVRS + AVX10
`VMOVRSW ymm {k}{z}, m256` 64-bit mode only VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512	`EVEX.256.F2.MAP5.W1 6F /r`	MOVRS + AVX10
`VMOVRSW zmm {k}{z}, m512` 64-bit mode only VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512	`EVEX.512.F2.MAP5.W1 6F /r`	MOVRS + AVX10

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

A masked move: each word is copied where its bit of k1 is 1; elsewhere merging keeps the old element, and zeroing writes 0.

merging, {k1}

zeroing, {k1}{z}

Example mask k1 = 0xB2. Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms.

With merging: result words 7 to 0: a7, unchanged, a5, a4, unchanged, unchanged, a1, unchanged.

With zeroing: result words 7 to 0: a7, 0, a5, a4, 0, 0, a1, 0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 31 & 1:
    fault(UD)  # CPUID: no MOVRS
if not cpuid_leaf(7, 1)[3] >> 19 & 1:
    fault(UD)  # CPUID: no AVX10
for i in range(VL // 16):
    if k1[i]:
        zmm1.w[i] = mem.w[i]
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases. Its cases ran where CPUID reported no MOVRS, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVRSW xmm {k}{z}, m128` 64-bit mode only `VMOVRSW ymm {k}{z}, m256` 64-bit mode only `VMOVRSW zmm {k}{z}, m512` 64-bit mode only
`xmm, ymm, zmm`	explicit	write (masked)
`{k}`	explicit	read (write mask)
`m128/256/512`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms: write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVRSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_loadrs_epi16` `__m128i _mm_loadrs_epi16(const void *__A)`	`VMOVRSW xmm, m128` EVEX.128 -mmovrs -mavx10.2
`_mm_mask_loadrs_epi16` `__m128i _mm_mask_loadrs_epi16(__m128i __W, __mmask8 __U, const void *__A)`	`VMOVRSW xmm {k}, m128` EVEX.128 -mmovrs -mavx10.2
`_mm_maskz_loadrs_epi16` `__m128i _mm_maskz_loadrs_epi16(__mmask8 __U, const void *__A)`	`VMOVRSW xmm {k}{z}, m128` EVEX.128 -mmovrs -mavx10.2
`_mm256_loadrs_epi16` `__m256i _mm256_loadrs_epi16(const void *__A)`	`VMOVRSW ymm, m256` EVEX.256 -mmovrs -mavx10.2
`_mm256_mask_loadrs_epi16` `__m256i _mm256_mask_loadrs_epi16(__m256i __W, __mmask16 __U, const void *__A)`	`VMOVRSW ymm {k}, m256` EVEX.256 -mmovrs -mavx10.2
`_mm256_maskz_loadrs_epi16` `__m256i _mm256_maskz_loadrs_epi16(__mmask16 __U, const void *__A)`	`VMOVRSW ymm {k}{z}, m256` EVEX.256 -mmovrs -mavx10.2
`_mm512_loadrs_epi16` `__m512i _mm512_loadrs_epi16(const void *__A)`	`VMOVRSW zmm, m512` EVEX.512 -mmovrs -mavx10.2
`_mm512_mask_loadrs_epi16` `__m512i _mm512_mask_loadrs_epi16(__m512i __W, __mmask32 __U, const void *__A)`	`VMOVRSW zmm {k}, m512` EVEX.512 -mmovrs -mavx10.2
`_mm512_maskz_loadrs_epi16` `__m512i _mm512_maskz_loadrs_epi16(__mmask32 __U, const void *__A)`	`VMOVRSW zmm {k}{z}, m512` EVEX.512 -mmovrs -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX10_MOVRS_128` MOVRS	MOVRS + AVX10 `CPUID.(EAX=07H,ECX=1):EAX[31]` MOVRS `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10	Nova Lake, Diamond Rapids
`AVX10_MOVRS_256` MOVRS	Same as `AVX10_MOVRS_128`	Same as `AVX10_MOVRS_128`
`AVX10_MOVRS_512` MOVRS	Same as `AVX10_MOVRS_128`	Same as `AVX10_MOVRS_128`

VMOVRSW