x86-64.net

Instruction

VMOVRSW

Loads a vector of words under a write mask, with a hint that other cores are likely to read the same data before it is written.

Extensions
Forms
3 (3 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVRSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVRSW xmm {k}{z}, m128 64-bit mode only VMOVRSW_XMMu16_MASKmskw_MEMu16_AVX512EVEX.128.F2.MAP5.W1 6F /rMOVRS + AVX10
VMOVRSW ymm {k}{z}, m256 64-bit mode only VMOVRSW_YMMu16_MASKmskw_MEMu16_AVX512EVEX.256.F2.MAP5.W1 6F /rMOVRS + AVX10
VMOVRSW zmm {k}{z}, m512 64-bit mode only VMOVRSW_ZMMu16_MASKmskw_MEMu16_AVX512EVEX.512.F2.MAP5.W1 6F /rMOVRS + AVX10

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVRSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_loadrs_epi16 __m128i _mm_loadrs_epi16(const void *__A)

VMOVRSW xmm, m128 EVEX.128 -mmovrs -mavx10.2

_mm_mask_loadrs_epi16 __m128i _mm_mask_loadrs_epi16(__m128i __W, __mmask8 __U, const void *__A)

VMOVRSW xmm {k}, m128 EVEX.128 -mmovrs -mavx10.2

_mm_maskz_loadrs_epi16 __m128i _mm_maskz_loadrs_epi16(__mmask8 __U, const void *__A)

VMOVRSW xmm {k}{z}, m128 EVEX.128 -mmovrs -mavx10.2

_mm256_loadrs_epi16 __m256i _mm256_loadrs_epi16(const void *__A)

VMOVRSW ymm, m256 EVEX.256 -mmovrs -mavx10.2

_mm256_mask_loadrs_epi16 __m256i _mm256_mask_loadrs_epi16(__m256i __W, __mmask16 __U, const void *__A)

VMOVRSW ymm {k}, m256 EVEX.256 -mmovrs -mavx10.2

_mm256_maskz_loadrs_epi16 __m256i _mm256_maskz_loadrs_epi16(__mmask16 __U, const void *__A)

VMOVRSW ymm {k}{z}, m256 EVEX.256 -mmovrs -mavx10.2

_mm512_loadrs_epi16 __m512i _mm512_loadrs_epi16(const void *__A)

VMOVRSW zmm, m512 EVEX.512 -mmovrs -mavx10.2

_mm512_mask_loadrs_epi16 __m512i _mm512_mask_loadrs_epi16(__m512i __W, __mmask32 __U, const void *__A)

VMOVRSW zmm {k}, m512 EVEX.512 -mmovrs -mavx10.2

_mm512_maskz_loadrs_epi16 __m512i _mm512_maskz_loadrs_epi16(__mmask32 __U, const void *__A)

VMOVRSW zmm {k}{z}, m512 EVEX.512 -mmovrs -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX10_MOVRS_128

MOVRS + AVX10
CPUID.(EAX=07H,ECX=1):EAX[31] MOVRS
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

Nova Lake, Diamond Rapids
AVX10_MOVRS_256

MOVRS + AVX10
CPUID.(EAX=07H,ECX=1):EAX[31] MOVRS
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

Nova Lake, Diamond Rapids
AVX10_MOVRS_512

MOVRS + AVX10
CPUID.(EAX=07H,ECX=1):EAX[31] MOVRS
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10

Nova Lake, Diamond Rapids

More MOVRS instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Architecture Instruction Set Extensions and Future Features Programming Reference (319433-062, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.