VMOVSD

VMOVSD is the VEX and EVEX form of MOVSD, whose page covers the scalar double move and the string instruction that shares its name. The load of eight bytes now clears the register up to bit 511, and the store is unchanged. The register form takes a second source: the low double comes from the last operand and the high double from the first source rather than from the destination, and bits 128 and up are cleared. VMOVSS covers what the two encodings share: two opcodes for the register form, no ymm form, vvvv at 1111b for the memory forms, AVX for VEX and AVX-512F or AVX10.1 for EVEX, whose write mask covers the one double. Zen 5’s recorded cases:

• {store} vmovsd xmm0, xmm13, xmm9, the 11h encoding, put the low double of XMM9 under the high double of XMM13 and cleared bits 511:128 of ZMM0.
• vmovsd xmm17{k1}{z}, qword ptr [mem], with bit 0 of K1 clear, left all of ZMM17 zero: the masked double is zeroed, and the load clears the rest in any case.
• vmovsd qword ptr [mem]{k6}, xmm7, with bit 0 of K6 clear, left the eight bytes alone.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 load and store double values with VMOVSD, except that GCC loads _mm_load_sd(p) with VMOVQ. _mm_set_sd(x) is vmovq xmm0, xmm0 in both, the zeroing register move that the scalar moves lack (VMOVQ). _mm_move_sd(a, b) is vmovsd xmm0, xmm0, xmm1 in GCC and vblendps xmm0, xmm0, xmm1, 3 in Clang. At -v4 Clang selects between two doubles with the write mask, vcmpltsd k1, xmm0, xmm1 and then vmovsd xmm3{k1}, xmm3, xmm2 for x < y ? a : b, as VMOVSS’s page shows for floats; GCC uses VCMPNLTSD and VBLENDVPD.

AMD’s latency spreadsheet for Zen 5 gives VMOVSD the cells of VMOVSS: one macro-op on pipes FP0 to FP3, a latency of 1 cycle, four per cycle in the VEX row and the EVEX register and store row, two per cycle in the EVEX load row.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    xmm1.q[0] = mem.q[0]
elif zeroing:
    xmm1.q[0] = 0
# else: xmm1.q[0] keeps its value
for i in range(1, 2):
    xmm1.q[i] = 0
# xmm1 is zeroed from bit 128 up

if k1[0]:  # 1 without a write mask
    mem.q[0] = xmm2.q[0]
# else: mem.q[0] is not written

if k1[0]:  # 1 without a write mask
    xmm1.q[0] = xmm3.q[0]
elif zeroing:
    xmm1.q[0] = 0
# else: xmm1.q[0] keeps its value
for i in range(1, 2):
    xmm1.q[i] = xmm2.q[i]
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMINSS
• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB

All 253 AVX instructions

More AVX10.1 instructions

• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW

All 686 AVX10.1 instructions