x86-64.net

Instruction

VMOVSD

Moves the low double between XMM registers or to and from memory; a load zeroes the rest of the register.

Extensions
Forms
7 (4 VEX, 3 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVSD xmm, m64 VMOVSD_XMMdq_MEMqVEX.LIG.F2.0F.WIG 10 /rAVX
VMOVSD m64, xmm VMOVSD_MEMq_XMMqVEX.LIG.F2.0F.WIG 11 /rAVX
VMOVSD xmm, xmm, xmm VMOVSD_XMMdq_XMMdq_XMMq_10VEX.LIG.F2.0F.WIG 10 /rAVX
VMOVSD xmm, xmm, xmm VMOVSD_XMMdq_XMMdq_XMMq_11VEX.LIG.F2.0F.WIG 11 /rAVX
VMOVSD xmm {k}{z}, m64 VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512EVEX.LIG.F2.0F.W1 10 /rAVX10.1 or AVX512F
VMOVSD m64 {k}, xmm VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512EVEX.LIG.F2.0F.W1 11 /rAVX10.1 or AVX512F
VMOVSD xmm {k}{z}, xmm, xmm VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512EVEX.LIG.F2.0F.W1 10 /r
EVEX.LIG.F2.0F.W1 11 /r		AVX10.1 or AVX512F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_load_sd __m128d _mm_load_sd(const double *__dp)

VMOVSD xmm, m64 VEX.LIG -mavxwith AVX enabled

_mm_store_sd void _mm_store_sd(double *__dp, __m128d __a)

VMOVSD m64, xmm VEX.LIG -mavxwith AVX enabled; Clang emits the equivalent VMOVLPD

_mm_mask_load_sd __m128d _mm_mask_load_sd(__m128d __W, __mmask8 __U, const double *__A)

VMOVSD xmm {k}, m64 EVEX.LIG -mavx512f

_mm_mask_move_sd __m128d _mm_mask_move_sd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B)

VMOVSD xmm {k}, xmm, xmm EVEX.LIG -mavx512f

_mm_mask_store_sd void _mm_mask_store_sd(double *__W, __mmask8 __U, __m128d __A)

VMOVSD m64 {k}, xmm EVEX.LIG -mavx512f

_mm_maskz_load_sd __m128d _mm_maskz_load_sd(__mmask8 __U, const double *__A)

VMOVSD xmm {k}{z}, m64 EVEX.LIG -mavx512f

_mm_maskz_move_sd __m128d _mm_maskz_move_sd(__mmask8 __U, __m128d __A, __m128d __B)

VMOVSD xmm {k}{z}, xmm, xmm EVEX.LIG -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_SCALAR

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.