VMOVSH

VMOVSH moves one half-precision value, the low 16 bits of an XMM register. Loading from memory, it writes the half to bits 15:0 and clears every bit above, up to bit 511; storing, it writes exactly two bytes; between registers, it takes the low half of the last operand and bits 127:16 of the middle one, and clears bits 128 and up. It is the FP16 member of the family of VMOVSS, which has the same three forms, and like it takes a write mask on the low element: zeroing or merging for the load and the register form, merging only for the store, which then writes nothing. VADDPH covers the format and the CPUID bits.

Encoding#

VMOVSH is EVEX-only, in map 5 with the F3 prefix, opcode 10h to load and 11h to store, the bytes of MOVSS in the old map. As for VMOVSS, both opcodes have a register form that does the same thing with the operands swapped in ModRM, which Intel’s entry calls aliases. VMOVW also moves 16 bits but takes no mask, reaches general-purpose registers, and always clears the rest of the register.

In our builds#

At -O2 with -march=x86-64-v4 -mavx512fp16, Clang 23 loads and stores _Float16 values and _mm_load_sh and _mm_store_sh with VMOVSH, while GCC 14 uses VMOVW for them. The register form is where both meet: _mm_move_sh(a, b) is vmovsh xmm0, xmm0, xmm1, and _mm_mask_move_sh the same with a mask from KMOVB or KMOVD. Both also use it as a select: a < b ? x : y on halves becomes a compare into K1 with VCMPSH and a masked VMOVSH that puts one value over the other, with no branch, and so does C’s fminf16 in Clang (see VMINSH).

AMD’s Zen 5 guide does not list AVX512-FP16, and this site’s recorded cases include none of VMOVSH.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:
    xmm1.w[0] = mem.w[0]
elif zeroing:
    xmm1.w[0] = 0
# else: xmm1.w[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = 0
# xmm1 is zeroed from bit 128 up

if k1[0]:
    mem.w[0] = xmm2.w[0]
# else: mem.w[0] is not written

if k1[0]:
    xmm1.w[0] = xmm3.w[0]
elif zeroing:
    xmm1.w[0] = 0
# else: xmm1.w[0] keeps its value
for i in range(1, 8):
    xmm1.w[i] = xmm2.w[i]
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VMOVD
• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB

All 686 AVX10.1 instructions