Instruction
VMOVSH
Moves the low half-precision value between XMM registers or to and from memory; a load zeroes the rest of the register.
- Extensions
- Forms
- 3 (3 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMOVSH xmm {k}{z}, m16
VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 | EVEX.LIG.F3.MAP5.W0 10 /r | AVX10.1 or AVX512_FP16 |
VMOVSH m16 {k}, xmm
VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 | EVEX.LIG.F3.MAP5.W0 11 /r | AVX10.1 or AVX512_FP16 |
VMOVSH xmm {k}{z}, xmm, xmm
VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 | EVEX.LIG.F3.MAP5.W0 10 /rEVEX.LIG.F3.MAP5.W0 11 /r | AVX10.1 or AVX512_FP16 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMOVSH, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_load_sbh
__m128bh _mm_load_sbh(const void *__dp) |
|
_mm_load_sh
__m128h _mm_load_sh(const void *__dp) |
|
_mm_move_sbh
__m128bh _mm_move_sbh(__m128bh __a, __m128bh __b) |
|
_mm_move_sh
__m128h _mm_move_sh(__m128h __a, __m128h __b) |
|
_mm_set_sbh
__m128bh _mm_set_sbh(__bf16 bf) |
|
_mm_set_sh
__m128h _mm_set_sh(_Float16 __h) |
|
_mm_store_sh
void _mm_store_sh(void *__dp, __m128h __a) |
|
_mm_mask_load_sh
__m128h _mm_mask_load_sh(__m128h __W, __mmask8 __U, const void *__A) |
|
_mm_mask_move_sh
__m128h _mm_mask_move_sh(__m128h __W, __mmask8 __U, __m128h __A, __m128h __B) |
|
_mm_mask_store_sh
void _mm_mask_store_sh(void *__W, __mmask8 __U, __m128h __A) |
|
_mm_maskz_load_sh
__m128h _mm_maskz_load_sh(__mmask8 __U, const void *__A) |
|
_mm_maskz_move_sh
__m128h _mm_maskz_move_sh(__mmask8 __U, __m128h __A, __m128h __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_SCALAR | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.