VMOVSHDUP

VMOVSHDUP is the VEX and EVEX form of MOVSHDUP: each odd single is copied over the even one below it, giving elements 1, 1, 3, 3 and so on across the register. MOVSHDUP’s page covers its uses, and VMOVSLDUP is the twin for the even singles. The VEX forms need AVX, ymm included; the EVEX forms need AVX-512F (with AVX512VL below 512 bits) or AVX10.1 and add a write mask per single, but no broadcast. There is still only one source, as VEX.vvvv and EVEX.vvvv must be 1111b; what changes is that memory needs no alignment and the register is cleared above the vector length. Since every pair stays where it is, the wider forms need no lanes: the ymm form is the xmm one twice.

Recorded on Zen 5#

• vmovshdup ymm7, ymm11 gave elements 1, 1, 3, 3, 5, 5, 7, 7 of YMM11.
• vmovshdup zmm7{k6}, zmm12, the low 16 bits of K6 43A4h, wrote elements 2, 5, 7, 8, 9 and 14 (elements 3, 5, 7, 9, 9 and 15 of ZMM12) and kept the other ten.
• vmovshdup xmm9{k6}{z}, xmmword ptr [mem] kept only element 2, the fourth single from memory, and zeroed the rest.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 and -v4, the shuffle __builtin_shufflevector(v, v, 1, 1, 3, 3, 5, 5, 7, 7) on eight floats is vmovshdup ymm0, ymm0 in Clang 23 but vpermilps ymm0, ymm0, 0xf5 in GCC 14, which uses the immediate form of VPERMILPS instead. GCC does the same in a float complex product with -fcx-limited-range, spreading the imaginary parts with F5h before a VFMADDSUB231PS.

AMD’s latency spreadsheet for Zen 5 gives VMOVSHDUP, in its VEX and EVEX rows alike, and that form of VPERMILPS the same figures: one macro-op with a latency of 1 cycle on any of the four vector pipes.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    j = i - i % 2 + 1
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVSHDUP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVAPD
• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD

All 253 AVX instructions

More AVX10.1 instructions

• VMOVDDUP
• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW

All 686 AVX10.1 instructions