VMOVSLDUP

VMOVSLDUP is the VEX and EVEX form of MOVSLDUP: each even single is copied over the odd one above it, giving elements 0, 0, 2, 2 and so on. VMOVSHDUP describes what the new encodings bring to both: ymm forms with AVX, zmm forms and a write mask per single with AVX-512F or AVX10.1, no broadcast, memory at any alignment, the register cleared above the vector length, and pairs that never cross a lane.

Recorded on Zen 5#

• {evex} vmovsldup ymm24, ymmword ptr [mem] gave singles 0, 0, 2, 2, 4, 4, 6, 6 of the 32 bytes, into a register only EVEX can name.
• vmovsldup ymm9{k5}{z}, ymm9, with the low byte of K5 E1h, read and wrote YMM9: element 0 was rewritten with itself, elements 5, 6 and 7 became elements 4, 6 and 6 of the old YMM9, and the other four were zeroed.
• vmovsldup xmm17{k2}{z}, xmmword ptr [mem], the low bits of K2 1001b, wrote the first single from memory to element 0 and the third to element 3, and zeroed elements 1 and 2.

The real parts of complex floats#

MOVSLDUP’s page shows GCC 14 spreading the real parts of a float complex product with MOVSLDUP. In our builds at -O2 with -march=x86-64-v3 -fcx-limited-range, GCC does the same work on eight singles with vpermilps ymm1, ymm0, 0xa0 instead, F5h for the imaginary parts and B1h to swap the parts of the other factor, and combines them with VMULPS and VFMADDSUB231PS; -v4 does the same on zmm registers. Multiplying by a real part only, GCC folds the load into vpermilps ymm0, ymmword ptr [...], 0xa0. Clang 23 separates real and imaginary parts with VSHUFPS and VPERMPD (VPERMT2PS at -v4) instead, and keeps VMOVSLDUP for the plain shuffle __builtin_shufflevector(v, v, 0, 0, 2, 2, 4, 4, 6, 6), which GCC spells vpermilps ymm0, ymm0, 0xa0.

AMD’s latency spreadsheet for Zen 5 gives VMOVSLDUP the figures of VMOVSHDUP in both rows: one macro-op, 1 cycle, four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    j = i - i % 2
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[j]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVSLDUP, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVAPS
• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ

All 253 AVX instructions

More AVX10.1 instructions

• VMOVDQA32
• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB

All 686 AVX10.1 instructions