Instruction
VMOVSS
Moves the low single between XMM registers or to and from memory; a load zeroes the rest of the register.
- Extensions
- Forms
- 7 (4 VEX, 3 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMOVSS xmm, m32
VMOVSS_XMMdq_MEMd | VEX.LIG.F3.0F.WIG 10 /r | AVX |
VMOVSS m32, xmm
VMOVSS_MEMd_XMMd | VEX.LIG.F3.0F.WIG 11 /r | AVX |
VMOVSS xmm, xmm, xmm
VMOVSS_XMMdq_XMMdq_XMMd_10 | VEX.LIG.F3.0F.WIG 10 /r | AVX |
VMOVSS xmm, xmm, xmm
VMOVSS_XMMdq_XMMdq_XMMd_11 | VEX.LIG.F3.0F.WIG 11 /r | AVX |
VMOVSS xmm {k}{z}, m32
VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 | EVEX.LIG.F3.0F.W0 10 /r | AVX10.1 or AVX512F |
VMOVSS m32 {k}, xmm
VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 | EVEX.LIG.F3.0F.W0 11 /r | AVX10.1 or AVX512F |
VMOVSS xmm {k}{z}, xmm, xmm
VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 | EVEX.LIG.F3.0F.W0 10 /rEVEX.LIG.F3.0F.W0 11 /r | AVX10.1 or AVX512F |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMOVSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_load_ss
__m128 _mm_load_ss(const float *__p) |
|
_mm_store_ss
void _mm_store_ss(float *__p, __m128 __a) |
|
_mm_mask_load_ss
__m128 _mm_mask_load_ss(__m128 __W, __mmask8 __U, const float *__A) |
|
_mm_mask_move_ss
__m128 _mm_mask_move_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) |
|
_mm_mask_store_ss
void _mm_mask_store_ss(float *__W, __mmask8 __U, __m128 __A) |
|
_mm_maskz_load_ss
__m128 _mm_maskz_load_ss(__mmask8 __U, const float *__A) |
|
_mm_maskz_move_ss
__m128 _mm_maskz_move_ss(__mmask8 __U, __m128 __A, __m128 __B) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX | AVX | Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2 |
AVX512F_SCALAR | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
More AVX10.1 instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.