VMOVSS

VMOVSS is the VEX and EVEX form of MOVSS, whose page covers the single-precision move and its uses in C. A load of four bytes now clears the register up to bit 511; the store is unchanged. The register form names two sources: the low single comes from the last, singles 1 to 3 from the first, and bits 128 and up are cleared, so vmovss xmm0, xmm2, xmm1 merges into a third register. As for MOVSD, opcodes 10h and 11h both encode it. There is no ymm form, and the load and store need vvvv at 1111b. The VEX form needs AVX; the EVEX form, AVX-512F or AVX10.1, adds a write mask on the single: a masked store with bit 0 clear writes nothing, and a masked load clears bits 32 and up whatever the mask says.

On Zen 5, vmovss xmm12, xmm6, xmm6 and its {store} twin, opcode 11h, both gave the low 128 bits of XMM6 and cleared bits 511:128 of ZMM12. vmovss xmm0{k4}{z}, dword ptr [mem], with bit 0 of K4 set, loaded the single and zeroed the rest of ZMM0, and vmovss dword ptr [mem]{k1}, xmm5, with bit 0 of K1 clear, left the four bytes as they were.

Merging and selecting#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 load and store float values with VMOVSS. For _mm_move_ss(a, b) GCC emits vmovss xmm0, xmm0, xmm1 and Clang vblendps xmm0, xmm0, xmm1, 1. The write mask appears at -v4, in Clang: c ? a : b on floats becomes SETE, KMOVD and vmovss xmm0{k1}, xmm0, xmm1, and x < y ? a : b becomes VCMPLTSS into K1 and a masked VMOVSS. GCC keeps a branch for the first and blends with VBLENDVPS for the second, as Clang does at -v3.

AMD’s latency spreadsheet for Zen 5 gives VMOVSS one macro-op on pipes FP0 to FP3 with a latency of 1 cycle: four per cycle in its VEX row and its EVEX row for registers and stores, two in its EVEX load row.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if k1[0]:  # 1 without a write mask
    xmm1.d[0] = mem.d[0]
elif zeroing:
    xmm1.d[0] = 0
# else: xmm1.d[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = 0
# xmm1 is zeroed from bit 128 up

if k1[0]:  # 1 without a write mask
    mem.d[0] = xmm2.d[0]
# else: mem.d[0] is not written

if k1[0]:  # 1 without a write mask
    xmm1.d[0] = xmm3.d[0]
elif zeroing:
    xmm1.d[0] = 0
# else: xmm1.d[0] keeps its value
for i in range(1, 4):
    xmm1.d[i] = xmm2.d[i]
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVD
• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB

All 253 AVX instructions

More AVX10.1 instructions

• VMOVDQA64
• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB

All 686 AVX10.1 instructions