VMOVUPD

VMOVUPD copies 16, 32 or 64 bytes between vector registers, or between a register and memory at any address, bits not interpreted. It is MOVUPD in VEX and EVEX encodings and the double-precision twin of VMOVUPS, whose page covers what the two share: the clearing above the vector width, masked loads that do not fault on the elements left out, the two register encodings and loop tails. VMOVAPD is the same move for aligned addresses. What the PD name changes is the mask: one bit per double.

Masks per double#

On Zen 5, vmovupd zmm1{k2}, zmmword ptr [mem] with C9H in the low byte of K2 loaded doubles 0, 3, 6 and 7 and kept the other four of ZMM1, and a store under E5H wrote doubles 0, 2, 5, 6 and 7 and left the rest of memory as it was. A 256-bit form reads only the low four mask bits: vmovupd ymm0{k1}{z}, ymm31 with A0H in K1 zeroed the whole register, since bits 3 to 0 were clear. The 17 recorded cases cover every form, all at a 64-byte aligned address.

In compiled code#

In our builds at -O2, both GCC 14 and Clang 23 load and store the doubles of a loop such as d[i] = s[i] * 2.0 with VMOVUPD: on ymm registers for -march=x86-64-v3, and for x86-64-v4 on zmm in GCC and ymm in Clang. For a tail of n doubles, a mask made with BZHI and _mm512_maskz_loadu_pd with _mm512_mask_storeu_pd give a zeroing VMOVUPD load and a masked VMOVUPD store under both compilers.

Alignment still counts#

The U only removes the fault. AMD’s Zen 5 guide says that a load or store crossing a 64-byte boundary costs at least a cycle and runs at half throughput, and one crossing a 4 KiB page can cost much more (Section 2.6.2; MOVDQU has the details). A zmm access is 64 bytes long, so at any address that is not a multiple of 64 it always spans two cache lines, where a ymm access does so only at some offsets.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        zmm1.q[i] = src2.q[i]
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        mem.q[i] = zmm2.q[i]
    # else: mem.q[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4M

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVUPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVDDUP
• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPS
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW

All 253 AVX instructions

More AVX10.1 instructions

• VMOVDQU16
• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPS
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD

All 686 AVX10.1 instructions