x86-64.net

Instruction

VMOVUPD

Moves packed doubles between registers and memory without an alignment requirement.

Extensions
Forms
17 (8 VEX, 9 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMOVUPD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMOVUPD xmm, m128 VMOVUPD_XMMdq_MEMdqVEX.128.66.0F.WIG 10 /rAVX
VMOVUPD xmm, xmm VMOVUPD_XMMdq_XMMdq_10VEX.128.66.0F.WIG 10 /rAVX
VMOVUPD m128, xmm VMOVUPD_MEMdq_XMMdqVEX.128.66.0F.WIG 11 /rAVX
VMOVUPD xmm, xmm VMOVUPD_XMMdq_XMMdq_11VEX.128.66.0F.WIG 11 /rAVX
VMOVUPD ymm, m256 VMOVUPD_YMMqq_MEMqqVEX.256.66.0F.WIG 10 /rAVX
VMOVUPD ymm, ymm VMOVUPD_YMMqq_YMMqq_10VEX.256.66.0F.WIG 10 /rAVX
VMOVUPD m256, ymm VMOVUPD_MEMqq_YMMqqVEX.256.66.0F.WIG 11 /rAVX
VMOVUPD ymm, ymm VMOVUPD_YMMqq_YMMqq_11VEX.256.66.0F.WIG 11 /rAVX
VMOVUPD zmm {k}{z}, zmm VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512EVEX.512.66.0F.W1 10 /r
EVEX.512.66.0F.W1 11 /r		AVX10.1 or AVX512F
VMOVUPD zmm {k}{z}, m512 VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512EVEX.512.66.0F.W1 10 /rAVX10.1 or AVX512F
VMOVUPD m512 {k}, zmm VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512EVEX.512.66.0F.W1 11 /rAVX10.1 or AVX512F
VMOVUPD xmm {k}{z}, xmm VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512EVEX.128.66.0F.W1 10 /r
EVEX.128.66.0F.W1 11 /r		AVX10.1 or AVX512F + AVX512VL
VMOVUPD xmm {k}{z}, m128 VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512EVEX.128.66.0F.W1 10 /rAVX10.1 or AVX512F + AVX512VL
VMOVUPD m128 {k}, xmm VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512EVEX.128.66.0F.W1 11 /rAVX10.1 or AVX512F + AVX512VL
VMOVUPD ymm {k}{z}, ymm VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512EVEX.256.66.0F.W1 10 /r
EVEX.256.66.0F.W1 11 /r		AVX10.1 or AVX512F + AVX512VL
VMOVUPD ymm {k}{z}, m256 VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512EVEX.256.66.0F.W1 10 /rAVX10.1 or AVX512F + AVX512VL
VMOVUPD m256 {k}, ymm VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512EVEX.256.66.0F.W1 11 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVUPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_loadu_pd __m128d _mm_loadu_pd(const double *__dp)

VMOVUPD xmm, m128 VEX.128 -mavxwith AVX enabled

_mm_storeu_pd void _mm_storeu_pd(double *__dp, __m128d __a)

VMOVUPD m128, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_loadu_pd __m128d _mm_mask_loadu_pd(__m128d __W, __mmask8 __U, const void *__P)

VMOVUPD xmm {k}, m128 EVEX.128 -mavx512vl

_mm_mask_storeu_pd void _mm_mask_storeu_pd(void *__P, __mmask8 __U, __m128d __A)

VMOVUPD m128 {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_loadu_pd __m128d _mm_maskz_loadu_pd(__mmask8 __U, const void *__P)

VMOVUPD xmm {k}{z}, m128 EVEX.128 -mavx512vl

_mm256_loadu_pd __m256d _mm256_loadu_pd(const double *__p)

VMOVUPD ymm, m256 VEX.256 -mavx

_mm256_storeu_pd void _mm256_storeu_pd(double *__p, __m256d __a)

VMOVUPD m256, ymm VEX.256 -mavx

_mm256_mask_loadu_pd __m256d _mm256_mask_loadu_pd(__m256d __W, __mmask8 __U, const void *__P)

VMOVUPD ymm {k}, m256 EVEX.256 -mavx512vl

_mm256_mask_storeu_pd void _mm256_mask_storeu_pd(void *__P, __mmask8 __U, __m256d __A)

VMOVUPD m256 {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_loadu_pd __m256d _mm256_maskz_loadu_pd(__mmask8 __U, const void *__P)

VMOVUPD ymm {k}{z}, m256 EVEX.256 -mavx512vl

_mm512_loadu_pd __m512d _mm512_loadu_pd(const void *__p)

VMOVUPD zmm, m512 EVEX.512 -mavx512f

_mm512_storeu_pd void _mm512_storeu_pd(void *__P, __m512d __A)

VMOVUPD m512, zmm EVEX.512 -mavx512f

_mm512_mask_loadu_pd __m512d _mm512_mask_loadu_pd(__m512d __W, __mmask8 __U, const void *__P)

VMOVUPD zmm {k}, m512 EVEX.512 -mavx512f

_mm512_mask_storeu_pd void _mm512_mask_storeu_pd(void *__P, __mmask8 __U, __m512d __A)

VMOVUPD m512 {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_loadu_pd __m512d _mm512_maskz_loadu_pd(__mmask8 __U, const void *__P)

VMOVUPD zmm {k}{z}, m512 EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.