VMOVUPS

VMOVUPS copies packed singles between vector registers, or between a register and memory at any address. Like MOVUPS, its SSE form, it does not interpret the bits, so compilers move any data with it: at -O2 with -march=x86-64-v3, GCC 14 and Clang 23 load and store the floats of vectorized loops with VMOVUPS, and Clang also uses it for _mm256_loadu_si256 and for a 32-byte memcpy, where GCC emits VMOVDQU. VMOVAPS is the same move for aligned addresses, and AMD’s Zen 5 guide says that on aligned data the two perform the same (Section 2.6.2).

What VEX and EVEX add#

• Clearing above the width. MOVUPS leaves bits 128 and up of its destination register alone; every VEX and EVEX form clears them above its own width. On Zen 5, vmovups xmm8, xmm15 left bits 128 to 511 of ZMM8 zero.
• Write masks. The EVEX forms (AVX512F, or AVX10.1) select singles with a mask register. A masked load keeps the unselected elements of the destination, or zeroes them with {z}; a masked store writes only the selected ones. Elements left out raise no fault, so a load may reach into an unmapped page past the end of an array.
• Two register encodings. Opcode 10 writes the register in ModRM.reg and 11 the one in ModRM.rm. GNU as and LLVM’s assembler pick 10, but take 11 where that fits the two-byte VEX prefix: vmovups xmm0, xmm15 becomes C5 78 11 F8.

Loop tails#

The masks let a loop finish without a scalar remainder: for a mask of the n low bits made with BZHI, _mm512_maskz_loadu_ps and _mm512_mask_storeu_ps compile to one VMOVUPS each under both compilers with -march=x86-64-v4. For a plain loop over 1,024 floats that target makes GCC 14 use zmm registers, while Clang 23 stays with ymm.

Zen 5’s 17 recorded cases cover every form, among them a masked vmovups zmm14{k6} load that kept the unselected singles of ZMM14 and a masked store that left the unselected memory as it was.

In the optimization guide

What the optimization guide says about VMOVUPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

• Cache lines, alignment and splits: In a stream of consecutive accesses that all start at the same misalignment, the share that splits a line grows with the width: one 16-byte access in four, every second 32-byte AVX access and every 64-byte AVX-512 access.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = src2.d[i]
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        mem.d[i] = zmm2.d[i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4M

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVUPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVDQA
• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMPSADBW
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB

All 253 AVX instructions

More AVX10.1 instructions

• VMOVDQU32
• VMOVDQU64
• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVW
• VMULPD
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ

All 686 AVX10.1 instructions