VMOVW instruction (AVX10.1, AVX10.2)

VMOVW moves one 16-bit word between the lowest element of an XMM register and a general-purpose register or memory. It is the word-sized member of the family of VMOVD and VMOVQ, added by AVX512-FP16 so that a half-precision value, or its bit pattern, can travel in one instruction. Loading, it writes the word to bits 15:0 and clears every other bit of the vector register up to bit 511; storing to a general-purpose register, it clears the register’s other bits.

Why a new move

Before AVX512-FP16 a word went into a vector register with VPINSRW, which keeps the rest of the destination and so depends on its old contents, and came out with VPEXTRW; VMOVD moves two words, reading or writing two bytes too many in memory. VMOVW avoids both costs: it breaks the dependency on the destination, as VMOVD does, and touches exactly two bytes. It is EVEX-only (EVEX.128 in map 5, opcodes 6E and 7E, those of MOVD in the old map), so it reaches XMM16 to XMM31, but it takes no mask. The FP16 scalar move between XMM registers and memory is VMOVSH, which can also merge with a mask.

In our builds

With -march=sapphirerapids, GCC 14 and Clang 23 at -O2 use VMOVW to reinterpret a _Float16 as its 16 bits and back through memcpy, and for _mm_cvtsi16_si128(); for _mm_cvtsi128_si16() Clang 23 emits VMOVW and GCC 14 VPEXTRW. Loading a _Float16 from memory, GCC 14 uses VMOVW and Clang 23 VMOVSH. With -march=znver5, which lacks AVX512-FP16, the same bit moves become VMOVD in GCC 14 and VPINSRW and VPEXTRW in Clang 23, and a load is a VPINSRW into whatever the register held.

Where it runs

VMOVW needs AVX512_FP16 (CPUID leaf 7, EDX bit 23) or AVX10.1, which includes it. AMD’s Zen 5 guide does not list AVX512-FP16 among Zen 5’s AVX-512 extensions, GCC 14 and Clang 23 leave it out of -march=znver5, and this site’s recorded cases include none of VMOVW.

Forms

Every encoding of VMOVW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMOVW xmm, r32` VMOVW_XMMf16_GPR32f16_AVX512	`EVEX.128.66.MAP5.WIG 6E /r`	AVX10.1 or AVX512_FP16
`VMOVW xmm, m16` VMOVW_XMMf16_MEMf16_AVX512	`EVEX.128.66.MAP5.WIG 6E /r`	AVX10.1 or AVX512_FP16
`VMOVW r32, xmm` VMOVW_GPR32f16_XMMf16_AVX512	`EVEX.128.66.MAP5.WIG 7E /r`	AVX10.1 or AVX512_FP16
`VMOVW m16, xmm` VMOVW_MEMf16_XMMf16_AVX512	`EVEX.128.66.MAP5.WIG 7E /r`	AVX10.1 or AVX512_FP16
`VMOVW xmm, xmm` VMOVW_XMMu16_XMMu16_AVX512_MOVZXC	`EVEX.128.F3.MAP5.W0 6E /r` `EVEX.128.F3.MAP5.W0 7E /r`	AVX10.2
`VMOVW xmm, m16` VMOVW_XMMu16_MEMu16_AVX512_MOVZXC	`EVEX.128.F3.MAP5.W0 6E /r`	AVX10.2
`VMOVW m16, xmm` VMOVW_MEMu16_XMMu16_AVX512_MOVZXC	`EVEX.128.F3.MAP5.W0 7E /r`	AVX10.2

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, r32`	`xmm, m16`	`r32, xmm`	`m16, xmm`
Sapphire Rapids	3 / 1p5	7 / 0.33p2 p3 p10	3 / 1p0	18 / 0.5p4789

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The word in r32 goes to the low end of xmm1, and the rest of xmm1 is zeroed.VMOVW xmm, r32 VMOVW xmm, m16

Result words 7 to 0: 0, 0, 0, 0, 0, 0, 0, a0.

The low word of xmm2 goes to r32, zero-extended.VMOVW r32, xmm VMOVW m16, xmm

r32 receives word 0 of xmm2: a0.

The low word of xmm2 goes to the low end of xmm1, and the rest of xmm1 is zeroed.VMOVW xmm, xmm

Result words 7 to 0: 0, 0, 0, 0, 0, 0, 0, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

VMOVW xmm, r32 VMOVW xmm, m16

xmm1.write(src2.w[0])  # zeroed from bit 16 up

Not run on a processor: none of these processors has AVX512-FP16 or AVX10.2.

VMOVW r32, xmm VMOVW m16, xmm

dest.write(xmm2.w[0])  # zero-extended in a register

Not run on a processor: none of these processors has AVX512-FP16 or AVX10.2.

VMOVW xmm, xmm

xmm1.write(xmm2.w[0])  # zeroed from bit 16 up

Not run on a processor: none of these processors has AVX10.2.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VMOVW xmm, r32`
`xmm`	explicit	write
`r32`	explicit	read
`VMOVW xmm, xmm/m16`
`xmm`	explicit	write
`xmm/m16`	explicit	read
`VMOVW r32, xmm`
`r32`	explicit	write
`xmm`	explicit	read
`VMOVW m16, xmm`
`m16`	explicit	write
`xmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMOVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtsi128_si16` `short _mm_cvtsi128_si16(__m128i __a)`	`VMOVW r32, xmm` EVEX.128 -mavx512fp16
`_mm_cvtsi16_si128` `__m128i _mm_cvtsi16_si128(short __a)`	`VMOVW xmm, r32` EVEX.128 -mavx512fp16
`_mm_move_epi16` `__m128i _mm_move_epi16(__m128i __A)`	`VMOVW xmm, xmm` EVEX.128 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512_FP16_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512_FP16 `CPUID.(EAX=07H,ECX=0):EDX[23]` AVX512_FP16	Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6
`AVX512_MOVZXC_128` AVX10.2	AVX10.2 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2` AVX10 version	Nova Lake, Diamond Rapids

AVX512_FP16_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512_FP16
CPUID.(EAX=07H,ECX=0):EDX[23] AVX512_FP16

Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 6

AVX512_MOVZXC_128

AVX10.2

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

More AVX10.2 instructions

All 96 AVX10.2 instructions

Why a new move#

In our builds#

Where it runs#