Instruction
VMOVW
Moves 16 bits between an XMM register and a general-purpose register or memory, zeroing the rest of an XMM destination; AVX10.2 adds an XMM-to-XMM form.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VMOVW xmm, r32
VMOVW_XMMf16_GPR32f16_AVX512 | EVEX.128.66.MAP5.WIG 6E /r | AVX10.1 or AVX512_FP16 |
VMOVW xmm, m16
VMOVW_XMMf16_MEMf16_AVX512 | EVEX.128.66.MAP5.WIG 6E /r | AVX10.1 or AVX512_FP16 |
VMOVW r32, xmm
VMOVW_GPR32f16_XMMf16_AVX512 | EVEX.128.66.MAP5.WIG 7E /r | AVX10.1 or AVX512_FP16 |
VMOVW m16, xmm
VMOVW_MEMf16_XMMf16_AVX512 | EVEX.128.66.MAP5.WIG 7E /r | AVX10.1 or AVX512_FP16 |
VMOVW xmm, xmm
VMOVW_XMMu16_XMMu16_AVX512_MOVZXC | EVEX.128.F3.MAP5.W0 6E /rEVEX.128.F3.MAP5.W0 7E /r | AVX10.2 |
VMOVW xmm, m16
VMOVW_XMMu16_MEMu16_AVX512_MOVZXC | EVEX.128.F3.MAP5.W0 6E /r | AVX10.2 |
VMOVW m16, xmm
VMOVW_MEMu16_XMMu16_AVX512_MOVZXC | EVEX.128.F3.MAP5.W0 7E /r | AVX10.2 |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VMOVW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtsi128_si16
short _mm_cvtsi128_si16(__m128i __a) |
|
_mm_cvtsi16_si128
__m128i _mm_cvtsi16_si128(short __a) |
|
_mm_move_epi16
__m128i _mm_move_epi16(__m128i __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512_FP16_128N | AVX10.1 or AVX512_FP16 | Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512_MOVZXC_128 | AVX10.2 | Nova Lake, Diamond Rapids |
More AVX10.1 instructions
- VMOVDQU64
- VMOVDQU8
- VMOVHLPS
- VMOVHPD
- VMOVHPS
- VMOVLHPS
- VMOVLPD
- VMOVLPS
- VMOVNTDQ
- VMOVNTDQA
- VMOVNTPD
- VMOVNTPS
- VMOVQ
- VMOVSD
- VMOVSH
- VMOVSHDUP
- VMOVSLDUP
- VMOVSS
- VMOVUPD
- VMOVUPS
- VMULPD
- VMULPH
- VMULPS
- VMULSD
- VMULSH
- VMULSS
- VORPD
- VORPS
- VPABSB
- VPABSD
- VPABSQ
- VPABSW
- VPACKSSDW
- VPACKSSWB
- VPACKUSDW
- VPACKUSWB
- VPADDB
- VPADDD
- VPADDQ
- VPADDSB
More AVX10.2 instructions
- VFMSUB231BF16
- VFNMADD132BF16
- VFNMADD213BF16
- VFNMADD231BF16
- VFNMSUB132BF16
- VFNMSUB213BF16
- VFNMSUB231BF16
- VFPCLASSBF16
- VGETEXPBF16
- VGETMANTBF16
- VMAXBF16
- VMINBF16
- VMINMAXBF16
- VMINMAXPD
- VMINMAXPH
- VMINMAXPS
- VMINMAXSD
- VMINMAXSH
- VMINMAXSS
- VMOVD
- VMPSADBW
- VMULBF16
- VPDPBSSD
- VPDPBSSDS
- VPDPBSUD
- VPDPBSUDS
- VPDPBUUD
- VPDPBUUDS
- VPDPWSUD
- VPDPWSUDS
- VPDPWUSD
- VPDPWUSDS
- VPDPWUUD
- VPDPWUUDS
- VRCPBF16
- VREDUCEBF16
- VRNDSCALEBF16
- VRSQRTBF16
- VSCALEFBF16
- VSQRTBF16
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.