VMPSADBW

VMPSADBW is the VEX form of SSE4.1’s MPSADBW, whose page covers the eight sliding sums of absolute differences and their use in motion estimation. The VEX encoding takes a separate destination, reads memory at any alignment and clears the register above the vector length; VEX.128 needs AVX and VEX.256 AVX2.

Two lanes, two controls#

The ymm form repeats the operation in each 128-bit lane, and each lane has its own fields in the immediate: bits 2:0 steer the low lane, as in the xmm form, and bits 5:3 the high lane, so only bits 7:6 are ignored. On Zen 5, the recorded vmpsadbw ymm8, ymm15, ymm0, 0x2c took the high lane’s block from its doubleword 1, as bits 4:3 = 01b select, and its windows from byte 4, as bit 5 selects. With zeros in that block and bytes 00h to 0Fh in the high lane of YMM15, words 8 to 15 came out as 16h, 1Ah and so on up to 32h, the plain byte sum of each window.

AVX10.2 adds EVEX forms at all three widths, with a write mask per word and a different prefix (F3 rather than 66); the 512-bit form gives its upper two lanes the controls of the lower two. Zen 5 has no AVX10.2, so the probe left them unrun.

In compiled code#

In our builds at -O2, _mm_mpsadbw_epu8 and _mm256_mpsadbw_epu8 compile to VMPSADBW in GCC 14 and Clang 23 with -march=x86-64-v3 and x86-64-v4. Clang 23 also accepts -mavx10.2 and compiles _mm512_mpsadbw_epu8 and its masked form to the EVEX zmm form; GCC 14 has no such option. The eight sums written as two loops over fixed-size global arrays are vectorized differently: Clang widens the windows with VPMOVZXBW and takes each difference as VPMAXUW minus VPMINUW, and neither compiler emits VMPSADBW.

AMD’s latency spreadsheet for Zen 5 gives every VEX row a latency of 5 cycles: four macro-ops and one every two cycles for the xmm register form, six and one every three with memory, three and four for the ymm register and memory forms, one every two cycles.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for l in range(VL // 128):       # each 128-bit lane
    c = imm8 >> 3 * l            # lane 1: imm8[5:3]
    p = 16 * l + 4 * (c >> 2 & 1)  # the windows of ymm2
    q = 16 * l + 4 * (c & 3)       # the block of src3
    for i in range(8):
        s = 0
        for j in range(4):
            x = ymm2.b[p + i + j]
            s += abs(x - src3.b[q + j])
        ymm1.w[8 * l + i] = s
# imm8[7:6] are ignored, and imm8[5:3] by the xmm forms
# ymm1 is zeroed from bit VL up

for l in range(VL // 128):       # each 128-bit lane
    c = imm8 >> 3 * (l % 2)      # lanes 1, 3: imm8[5:3]
    p = 16 * l + 4 * (c >> 2 & 1)  # the windows of zmm2
    q = 16 * l + 4 * (c & 3)       # the block of src3
    for i in range(8):
        s = 0
        for j in range(4):
            x = zmm2.b[p + i + j]
            s += abs(x - src3.b[q + j])
        if k1[8 * l + i]:        # 1 without a write mask
            zmm1.w[8 * l + i] = s
        elif zeroing:
            zmm1.w[8 * l + i] = 0
        # else: the word keeps its value
# imm8[7:6] are ignored
# src3 is read whatever the mask: a fault in it is not
# suppressed
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMPSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVDQU
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMULPD
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW

All 253 AVX instructions

More AVX2 instructions

• VBROADCASTI128
• VBROADCASTSD
• VBROADCASTSS
• VEXTRACTI128
• VGATHERDPD
• VGATHERDPS
• VGATHERQPD
• VGATHERQPS
• VINSERTI128
• VMOVNTDQA
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW
• VPALIGNR
• VPAND
• VPANDN
• VPAVGB
• VPAVGW
• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ

All 138 AVX2 instructions

More AVX10.2 instructions

• VFNMADD132BF16
• VFNMADD213BF16
• VFNMADD231BF16
• VFNMSUB132BF16
• VFNMSUB213BF16
• VFNMSUB231BF16
• VFPCLASSBF16
• VGETEXPBF16
• VGETMANTBF16
• VMAXBF16
• VMINBF16
• VMINMAXBF16
• VMINMAXPD
• VMINMAXPH
• VMINMAXPS
• VMINMAXSD
• VMINMAXSH
• VMINMAXSS
• VMOVD
• VMOVW
• VMULBF16
• VPDPBSSD
• VPDPBSSDS
• VPDPBSUD
• VPDPBSUDS
• VPDPBUUD
• VPDPBUUDS
• VPDPWSUD
• VPDPWSUDS
• VPDPWUSD
• VPDPWUSDS
• VPDPWUUD
• VPDPWUUDS
• VRCPBF16
• VREDUCEBF16
• VRNDSCALEBF16
• VRSQRTBF16
• VSCALEFBF16
• VSQRTBF16
• VSUBBF16

All 96 AVX10.2 instructions