x86-64.net

Instruction

VMPSADBW

Computes, per 128-bit lane, word sums of absolute differences between a 4-byte block of the second source and eight sliding blocks of the first.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMPSADBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMPSADBW xmm, xmm, m128, imm8 VMPSADBW_XMMdq_XMMdq_MEMdq_IMMbVEX.128.66.0F3A.WIG 42 /r ibAVX
VMPSADBW xmm, xmm, xmm, imm8 VMPSADBW_XMMdq_XMMdq_XMMdq_IMMbVEX.128.66.0F3A.WIG 42 /r ibAVX
VMPSADBW ymm, ymm, m256, imm8 VMPSADBW_YMMqq_YMMqq_MEMqq_IMMbVEX.256.66.0F3A.WIG 42 /r ibAVX2
VMPSADBW ymm, ymm, ymm, imm8 VMPSADBW_YMMqq_YMMqq_YMMqq_IMMbVEX.256.66.0F3A.WIG 42 /r ibAVX2
VMPSADBW xmm {k}{z}, xmm, xmm, imm8 VMPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512EVEX.128.F3.0F3A.W0 42 /r ibAVX10.2
VMPSADBW xmm {k}{z}, xmm, m128, imm8 VMPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512EVEX.128.F3.0F3A.W0 42 /r ibAVX10.2
VMPSADBW ymm {k}{z}, ymm, ymm, imm8 VMPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512EVEX.256.F3.0F3A.W0 42 /r ibAVX10.2
VMPSADBW ymm {k}{z}, ymm, m256, imm8 VMPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512EVEX.256.F3.0F3A.W0 42 /r ibAVX10.2
VMPSADBW zmm {k}{z}, zmm, zmm, imm8 VMPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512EVEX.512.F3.0F3A.W0 42 /r ibAVX10.2
VMPSADBW zmm {k}{z}, zmm, m512, imm8 VMPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512EVEX.512.F3.0F3A.W0 42 /r ibAVX10.2

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMPSADBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_mpsadbw_epu8 __m128i _mm_mpsadbw_epu8(__m128i X, __m128i Y, const int M)

VMPSADBW xmm, xmm, xmm, imm8 VEX.128 -mavxwith AVX enabled

_mm_mask_mpsadbw_epu8 __m128i _mm_mask_mpsadbw_epu8(__m128i W, __mmask8 U, __m128i A, __m128i B, const int imm)

VMPSADBW xmm {k}, xmm, xmm, imm8 EVEX.128 -mavx10.2

_mm_maskz_mpsadbw_epu8 __m128i _mm_maskz_mpsadbw_epu8(__mmask8 U, __m128i A, __m128i B, const int imm)

VMPSADBW xmm {k}{z}, xmm, xmm, imm8 EVEX.128 -mavx10.2

_mm256_mpsadbw_epu8 __m256i _mm256_mpsadbw_epu8(__m256i X, __m256i Y, const int M)

VMPSADBW ymm, ymm, ymm, imm8 VEX.256 -mavx2

_mm256_mask_mpsadbw_epu8 __m256i _mm256_mask_mpsadbw_epu8(__m256i W, __mmask16 U, __m256i A, __m256i B, const int imm)

VMPSADBW ymm {k}, ymm, ymm, imm8 EVEX.256 -mavx10.2

_mm256_maskz_mpsadbw_epu8 __m256i _mm256_maskz_mpsadbw_epu8(__mmask16 U, __m256i A, __m256i B, const int imm)

VMPSADBW ymm {k}{z}, ymm, ymm, imm8 EVEX.256 -mavx10.2

_mm512_mpsadbw_epu8 __m512i _mm512_mpsadbw_epu8(__m512i A, __m512i B, const int imm)

VMPSADBW zmm, zmm, zmm, imm8 EVEX.512 -mavx10.2

_mm512_mask_mpsadbw_epu8 __m512i _mm512_mask_mpsadbw_epu8(__m512i W, __mmask32 U, __m512i A, __m512i B, const int imm)

VMPSADBW zmm {k}, zmm, zmm, imm8 EVEX.512 -mavx10.2

_mm512_maskz_mpsadbw_epu8 __m512i _mm512_maskz_mpsadbw_epu8(__mmask32 U, __m512i A, __m512i B, const int imm)

VMPSADBW zmm {k}{z}, zmm, zmm, imm8 EVEX.512 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512_MEDIAX_128

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MEDIAX_256

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids
AVX512_MEDIAX_512

AVX10.2
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 2 AVX10 version

Nova Lake, Diamond Rapids

More AVX10.2 instructions

All 96 AVX10.2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.