Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of VMPTRLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VMPTRLD m64 VMPTRLD_MEMqNP 0F C7 /6VMX

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not in_vmx:
    fault(UD)
if vmx_nonroot:
    vm_exit(21)                  # the hypervisor emulates it
if CPL > 0:
    fault(GP, 0)
p = src.read()                   # a physical address
basic = msr[IA32_VMX_BASIC]
w = maxphyaddr                   # the physical-address width, or
if basic >> 48 & 1:              # 32 bits where IA32_VMX_BASIC[48]
    w = 32                       # says so
if p & 0xFFF or p >> w:
    vm_fail(9)                   # not 4-KByte aligned, or past the
                                 # physical-address width
elif p == vmxon_ptr:
    vm_fail(10)                  # the VMXON region is no VMCS
else:
    r = phys_read(p, 32)         # the region's revision identifier
    caps = msr[IA32_VMX_PROCBASED_CTLS2]
    shadow = caps >> 46 & 1      # VMCS shadowing may be 1
    if r & 0x7FFFFFFF != basic & 0x7FFFFFFF:
        vm_fail(11)
    elif r >> 31 and not shadow:
        vm_fail(11)              # a shadow VMCS, which only VMCS
                                 # shadowing uses
    else:
        current_vmcs = p
        vm_succeed()

Run on AMD Zen 5 (EPYC 9645): 2 cases. Its cases ran where CPUID reported no VMX, and every one raised an exception.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VMPTRLD m64
m64explicitread
RFLAGSimplicitwrite

Flags

M modified, 0 cleared; blank: not affected. How to read.
OFSFZFAFPFCF
All forms
00M00M

Attributes

What else XED records about the forms. How to read.

All forms
privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
VTX

VMX
CPUID.01H:ECX[5] VMX

Core (Merom, Conroe), Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Bonnell, Saltwell, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill

Note: XED's AMD chips, which it derives from its Intel chips, have VMX too; AMD processors implement AMD-V (SVM) instead, so this list leaves them out.

More VMX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026): Volume 3C, page 33-17 (VMPTRLD)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.