VMSAVE instruction (SVM)

Forms

Every encoding of VMSAVE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VMSAVE` VMSAVE	`0F 01 DB`	SVM

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not efer >> 12 & 1:
    fault(UD)                    # EFER.SVME clear: SVM off
if CPL > 0:
    fault(GP, 0)
if intercepted(0x83):
    vm_exit(0x83)                # in a guest: to its hypervisor
a = rax                          # the VMCB's physical address (EAX
                                 # with a 67 prefix)
if a & 0xFFF or a >> maxphyaddr:
    fault(GP, 0)
vmcb_save_segments(a)            # FS, GS, LDTR and TR, each with
                                 # its hidden parts
phys_write(a + 0x600, 64, star)
phys_write(a + 0x608, 64, lstar)
phys_write(a + 0x610, 64, cstar)
phys_write(a + 0x618, 64, fmask)
phys_write(a + 0x620, 64, kernel_gs_base)
phys_write(a + 0x628, 64, sysenter_cs)
phys_write(a + 0x630, 64, sysenter_esp)
phys_write(a + 0x638, 64, sysenter_eip)

Run on AMD Zen 5 (EPYC 9645): 2 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms: not in real-address mode

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SVM` SVM	SVM `CPUID.80000001H:ECX[2]` SVM	K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

VMSAVE