VMULPD

VMULPD multiplies doubles, two, four or eight at a time. It is MULPD in VEX and EVEX encodings; VMULPS covers what they add and how compilers fuse a multiplication and an addition into an FMA, which happens to doubles in the same way.

Rounding modes on Zen 5#

The cases recorded on Zen 5 show how much the rounding mode can matter for a double:

• With MXCSR set to round toward zero, 0.1 times 3 gave 3FD3333333333333H, the double just below the exact product, and 10^300 times 10^300 gave the largest finite double rather than infinity.
• With MXCSR rounding up, the square of -2^-1023 gave the smallest denormal, 2^-1074, rather than 0.
• {rd-sae} overrides MXCSR for one 512-bit instruction: with MXCSR at round to nearest, 0.1 times 0.1 gave 3F847AE147AE147BH, rounded down. DAZ still applies: a denormal input squared gave 0.
• {rn-sae} with every exception unmasked squared the largest double to infinity without #XM and left MXCSR’s flags alone; without it, a signaling NaN under MXCSR 0 raised #XM and left the destination as it was.

Division by a constant#

A division by a power of two is a multiplication by its exact reciprocal, so GCC 14 and Clang 23 at -O2 compile a[i] = b[i] / 2.0 over doubles to VMULPD by 0.5, with -march=x86-64-v3 and without any fast-math option. b[i] / 3.0 and b[i] / 0.1 stay VDIVPD, since 1/3 and 1/0.1 are not exact doubles; -ffast-math turns them into VMULPD by 0.333… and by 10, which can differ in the last bit. b[i] * 2.0 becomes VADDPD of b[i] to itself.

AMD’s Zen 5 guide lists VMULPD with the figures of VMULPS: a latency of 3 cycles on pipes FP0 and FP1, two per cycle.

In the optimization guide

What the optimization guide says about VMULPD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Haswell and Broadwell

• What Broadwell changed: Broadwell cuts the latency of floating-point multiplication from 5 cycles to 3, for SSE and AVX code and, by Intel’s manual, x87 as well; FMA stays at 5. sources differ

Zen and Zen+

• Vectors and floating point: A float addition takes three cycles, a multiplication three in single precision and four in double, and an FMA five, each on two pipes; AMD’s spreadsheet, LLVM’s model and Agner Fog agree.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:  # 1 without a write mask
        a = zmm2.f64[i]
        b = src3.f64[i]
        zmm1.f64[i] = mul(a, b)
    elif zeroing:
        zmm1.f64[i] = 0
    # else: zmm1.f64[i] keeps its value
# m64bcst: src3.f64[i] is the m64 for every i
# {er}: the form's rounding, not MXCSR.RC, and no flags
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-2

EVEX forms

AVX512-E2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VMULPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVMSKPD
• VMOVMSKPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMPSADBW
• VMULPS
• VMULSD
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW
• VPADDUSB
• VPADDUSW
• VPADDW

All 253 AVX instructions

More AVX10.1 instructions

• VMOVDQU8
• VMOVHLPS
• VMOVHPD
• VMOVHPS
• VMOVLHPS
• VMOVLPD
• VMOVLPS
• VMOVNTDQ
• VMOVNTDQA
• VMOVNTPD
• VMOVNTPS
• VMOVQ
• VMOVSD
• VMOVSH
• VMOVSHDUP
• VMOVSLDUP
• VMOVSS
• VMOVUPD
• VMOVUPS
• VMOVW
• VMULPH
• VMULPS
• VMULSD
• VMULSH
• VMULSS
• VORPD
• VORPS
• VPABSB
• VPABSD
• VPABSQ
• VPABSW
• VPACKSSDW
• VPACKSSWB
• VPACKUSDW
• VPACKUSWB
• VPADDB
• VPADDD
• VPADDQ
• VPADDSB
• VPADDSW

All 686 AVX10.1 instructions